| 9th IEEE International On-Line Testing Symposium |  |
| Kos International Convention Center, Kos Island, Greece
July 7-9, 2003 |
Monday July 7th, 2003 07.30 - 08.30 Registration 08.30 - 08.40 Welcome Message 08.40 - 10.00 Keynote Session
Moderator: Y.Zorian, Virage Logic
1. Challenges and Opportunities for FPGA Programmable System Platforms,
Ivo Bolsen, Xilinx
2. Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon Devices,
Robert Baumann, Texas Instruments10.00 - 10.15 Coffee Break 10.15 - 11.15 Session 1: On-Line Testing Approaches
Moderator: A. Paschalis, U. Athens
Coordinator: H. Levendel, Motorola1.1. Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error,
Y. Zhao, S. Dey, U. of California1.2. A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs,
Y. Tsiatouhas, S. Matakias, A. Arapoyanni, Th. Haniotakis, U. of Ioannina, U. of Athens, Southern Illinois U.1.3. On-Line Error Detection Constant Delay Adder,
W.J. Townsend, J. Abraham, P.K. Lala, U. of Texas, U. of Arkansas11.15 - 11.30 Coffee Break 11.30 - 12.30 Session 2: Self Checking Circuits
Moderator: R. Stefanelli, Politecnico di Milano
Coordinator: K. Roy, Purdue U.2.1. A Modulo p Checked Self-Checking Carry Select Adder,
V. Ocheretnij, M. Gössel, E.S. Sogomonyan, D. Marienfeld, U. of Potsdam2.2. Foundation of Combined Datapath and Controller Self-checking,
P. Oikonomakos, M. Zwolinski, U. of Southampton2.3. Synthesis of Low-Cost Parity-Based Partially Self-checking Circuits,
K. Mohanram, E.S. Sogomonyan, M. Gössel, N.A. Touba, U. of Texas at Austin, U. of Potsdam12.30 - 14.00 Lunch 14.00 - 15.00 Session 3: Checker Designs
Moderator: M. Gössel, Postdam U.
Coordinator: G. Cardarilli, U. Roma23.1. A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers,
S. Tarnick, SATCON GmbH3.2. Designing FPGA Base Self-Testing Checker for m-out-of-n Codes,
A. Mastrosova, V. Ostrovsky, I. Levin, K. Nikitin, Tomsk State U., Tel Aviv U.3.3. An Analog Checker with Input-Relative Tolerance for Duplicate Signals,
Haralampos G.,D. Stratigopoulos, Y. Makris, Yale U.15.00 - 15.15 Coffee Break 15.15 - 16.15 Session 4: Fault Tolerance
Moderator: J. Abraham, U. of Texas at Austin
Coordinator: R. Velazco, TIMA4.1. Further Studies on Power Consumption of Fault Tolerant Codes: The Active Elements,
D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland, C. Metra, U. of Bologna, Philips Research Laboratories4.2. On the Probability of Detecting Errors Generated by Permanent Faults Using Time Redundancy,
J. Aidemark, P. Folkesson, J. Karlsson, Chalmers U.T.4.3. The Positive Effect on IC Yield of Embedded Fault Tolerance for SEU's,
A. Nieuwland, R.P. Kleihorst, Philips Research Laboratories16.15 - 16.30 Coffee Break 16.30 - 17.30 Panel Session 1: How Can Defect-Based Test Be Made to Work in a Foundry World ?
Organizers: R. Aitken, Artisan Components
Panelists: Rob Aitken, Artisan Components
Cecilia Metra, U. Bologna
T.M. Mak, Intel
Jaume Segura, U. Illes Balears
Yervant Zorian, Virage Logic19.30 - Welcome Dinner -
Tuesday, July 8th, 2003 08.30 - 09.30 Session 5: Built In Self Test and Self Repair
Moderator: C. Landrault, LIRMM
Coordinator: G. Stamoulis, Crete U.5.1. On-line Testable Decimation Filter for Mixed-Signal BIST,
M.A. Naal, E. Simeu, S. Mir, TIMA5.2. An Efficient BIST Scheme for High-Speed Adders,
D.G. Nikolos, D. Nikolos, H.T. Vergos, C. Efstathiou, U. of Patras, TEI of Athens5.3. Memory Built-In Self-Repair for Nanotechnologies,
M. Nicolaidis, N. Achouri, L. Anghel, IRoC Technologies, TIMA09.30 - 09.45 Coffee Break 09.45 - 10.45 Session 6: Analysis and Modelling of Transient and Delay Faults
Moderator: A. Chatterjee, Georgia Institute of Technology
Coordinator: Y. Maidon, U. Bordeaux6.1. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits,
M. Sonza Reorda, M. Violante, Politecnico di Torino6.2. An Improved Markov Source Design for Scan BIST,
B. Yu, W. Li, S.M. Reddy, I. Pomeranz, U. of Iowa, Purdue U.6.3. Model for Transient Fault Propagation in Combinational Logic,
M. Omaña, G. Papasso, D. Rossi, C. Metra, U. of Bologna10.45 - 11.00 Coffee Break 11.00 - 12.00 Session 7: Analysis and Verification of FPGA Faults
Moderator: A. Salsano, U. Roma2
Coordinator: A. Veneris, Ottawa U.7.1. Analyzing SEU Effects in SRAM-based FPGAs,
M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, U. of Padova, I.N. di Fisica Nucleare, Politecnico di Torino7.2. Defect Analysis for Delay-Fault BIST in FPGAs,
P. Girard, O. Héron, S. Pravossoudovitch, M. Renovell, U. of Montpellier II, LIRMM7.3. A Fault Injection Tool for Xilinx FPGAs,
M. Alderighi, S. D'Angelo, M. Mancini, G.R. Sech, IASF - CNR12.00 - 14.00 Lunch 14.00 - 15.00 Session 8: On-Line Testing of Microprocessor-Based Systems
Moderator: H-J. Wunderlick, Stuttgard U.
Coordinator: F. Vargas, PUCRS8.1. Low-Cost On-Line Fault Detection Using Control Flow Assertions,
R. Venkatasubramanian, J.P. Hayes, B.T. Murray, U. of Michigan, Brighton Technical Center8.2. A Watchdog Processor to Detect Data and Control Flow Errors,
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, Politecnico di Torino8.3. Low-Cost On-Line Software-Based Self-Testing of Embedded Processor Cores,
G. Xenoulis, D. Gizopoulos, N. Kranitis, A. Paschalis, U. of Piraeus, U. of Athens15.00 - 15.15 Coffee Break 15.15 - 16.25 Session 9: Posters
Moderator: C. Papachristou, Case Western Reserve U.9.1. On Compaction-Based Concurrent Error Detection,
S. Almukhaizim, P. Drineas, Y. Makris, Yale U., Rensselaer Polytecnic Institute9.2. Increasing Implementability of B-driven Threshold Checkers,
V. Varshavsky, I. Levin, V. Ostrovsky, Tel Aviv U.9.3. RT-Level Concurrent Error Detection Technique for Data Dominated Systems,
O. Goloubeva, M. Sonza Reorda, M. Violante, Politecnico di Torino9.4. FAUST: FAUlt-injection Script-based Tool,
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, I. Solcia, L. Tagliaferri, Politecnico di Torino9.5. Fault Injection in Digital Logic Circuits at the VHDL Level,
S.R. Seward, P.K. Lala, U. of Arkansas9.6. Radiation Test Methodology for SRAM-Based FPGAs by Using THESIC+,
M. Alderighi, F. Casini, S. D'Angelo, F. Faure, M. Mancini, S. Pastore, G.R. Sechi, R. Velazco, IASF - CNR, Sanitas E.G.S.r.l., TIMA, Politecnico di Torino9.7. SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They Good Remedy ?
F. Vargas, D. Brum, D. Prestes, L. Bolzani, E. Rhod, M. Sonza Reorda, PUCRS9.8. Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems,
F.M. Gonçalves, M.B. Santos, I.P. Teixeira, J.P. Teixeira, IST/INESC-ID9.9. Analysis of Bit Transition Count For EDAC Encoded FSM,
N. Venkateswaran, V. Balaji, V. Mahalingam, T.L. Rajaprabhu, Foundation WARF9.10. A Configurable Built in Current Sensor for Mixed Signal Circuit Testing,
R. Picos, J. Font, E. Isern, M. Roca, E. Garcia, U. Illes Balears9.11. Functional Fault Collapsing in Combinational Logic Circuits Using Conventional ATPG,
A. Veneris, R. Chang, E. Amyeen, M. S. Abadir, W. K. Fuchs, S. Seyedi, U. of Toronto, Purdue U., Motorola, Cornell U.9.12. Evaluation of the Quality of Testing Path Delay Faults Under Restricted Input Assumption,
A. Krasniewski, Warsaw U.T.17.00 - Social Event (Tour and Gala Dinner) -
Wednesday, July 9th, 2003 08.30 - 09.30 Session 10: On-Line and Off-Line Testing
Moderator: S. Hellebrand, U. of Innsbruck
Coordinator: A. Krasniewski, Warsaw U.T.10.1. Control Signal Protection - A New Challenge for High Performance Processors,
M. Pflanz, H.T. Vierhaus, IBM Deutschland Entwicklung GmbH, Brandenburg U.T. Cottbus10.2. Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing,
B. Alorda, J. Segura, U. Illes Balears10.3. Perspectives of Combining On-line and Off-line Test Technology for Dependable Systems on a Chip,
H.T. Vierhaus, C. Galke, M. Pflanz, Brandenburg U.T. Cottbus, IBM Deutschland Entwicklung GmbH09.30 - 09.45 Coffee Break 09.45 - 10.45 Panel Session 2: When Will Soft Errors Be a Design Constraint ?
Organizers: E. Dupont, iRoC Technologies
Moderator: Y.Zorian, Virage Logic
Co-organized with IEEE Design & Test of Computers
Panelists:
(to include)R. Bauman, Texas Instruments
N. Seifert, HP
M. Nicolaïdis, iRoC Technologies
A. Neuwland, Philips Reserach Labs10.45 - 11.00 Coffee Break 11.00 - 12.00 Session 11: Industrial Application Cases
Moderator: E. Boehl, Robert Bosch GmbH
Coordinator: S. van Dijk, Philips Reserach Labs11.1. On a Redundant Diversified Steering Angle Sensor,
E. Dilger, M. Gulbins, T. Ohnesorge, B. Straube, Robert Bosch GmbH, Fraunhofer-Institut für Integrierte Schaltungen11.2. Automatic Toolset for Fault Tolerant Design: Results Demonstration on a Running Industrial Application,
A. Manzone, C. Gent, Centro Ricerche FIAT11.3. Software Error Injection Based Failure Characterization of the IEEE 1394 Bus,
D.J. Beauregard, Z. Kalbarczyk, R.K. Iyer, S. Chau, L. Alkalai, U. of Illinois, Jet Propulsion Laboratory-NASA12.00 - 14.00 Lunch 14.00 - 15.00 Session 12: Advanced Testing and Repair Issues
Moderator: R. Kleihorst, Philips Research Laboratories
Coordinator: P. Girard, LIRMM12.1. A Methodology to Test Replacement Solutions of Obsolete Processors,
R. Velazco, L. Anghel, S. Saleh, TIMA12.2. Crosstalk Effect Minimization for Encoded Busses,
L. Di Silvio, D. Rossi, C. Metra, U. of Bologna12.3. InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs,
D. Kagaris, S. Tragoudas, Southern Illinois U.15.00 End of IOLTS 2003 Program
IEEE Computer Society
Test Technology Technical Council