| 11th IEEE International On-Line Testing Symposium |  |
| Mercure Hotel, Saint Raphael, French Riviera, France July 6-8, 2005 |
| Wednesday July 6th, 2005 | |
| 07.30 - 08.30 | Registration |
| 08.30 - 08.45 | Welcome Message General Co-Chairs: L. Anghel, M. Nicolaidis Program Co-Chairs: C. Metra, K.Roy |
| 08.45 - 9.30 | Keynote Session |
| 09.30 - 09.45 |  |
| 9.45 - 10.45 | Session 1: Transient Fault Modeling and Analysis Moderators: N. Seifert, Intel Corporation V. Chalendar, TI, Sofia Antipolis |
| 1.1. | Analytical Semi-empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits, Tino Heijmen (Philips Research Laboratories) |
| 1.2. | Electrical Modeling for Laser Testing with Different Pulse Durations, A. Douin, V. Pouget, D. Lewis, P. Fouillat, P. Perdu (IXL Laboratory, CNES) |
| 1.3. | Analysing the Effectiveness of Fault Handling Procedures, P. Gawkowski, J. Sosnowski, B. Radko (Warsaw University of Technology) |
| 10.45 - 11.00 | |
| 11.00 - 12.00 | Session 2: Transient Faults' Hardening Techniques Moderators: J. Hayes, University of Michigan A. Salsano, Univeristy of Tor Vergata, Roma |
| 2.1. | On Transistor Level Gate Sizing for Increased Robustness to Transient Faults, J.M. Cazeaux, D. Rossi, M. Omana, C. Metra (University of Bologna), Abhijit Chatterjee (Gerorgia Institute of Technology) |
| 2.2. | On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study, Cristiano Lazzari (Universidade Federal do Rio Grande do Sul), Lorena Anghel (TIMA Laboratory), Ricardo A.L. Reis (Universidade Federal do Rio Grande do Sul) |
| 2.3. | Output Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits, Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee (Georgia Institute of Technology), Cecilia Metra (University of Bologna) |
| 12.00 - 14.00 | Lunch |
| 14.00 - 15.00 | Session 3: SEU Effects in FPGAs Moderators: P. Girard, LIRMM M. Lubaszewski, UFRGS |
| 3.1. | Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading, Celia López Ongil, Mario García Valderas, Marta Portela García, Luis Entrena Arrontes (University Carlos III of Madrid) |
| 3.2. | Heavy Ion Effects on Configuration Logic of Virtex FPGAs, M. Alderighi, A. Candelori, F. Casini, S. D’Angelo, M. Mancini, A. Paccagnella, S. Pastore, G.R. Sechi, (Istituto di Astrofisica Spaziale e Fisica Cosmica, Istituto Nazionale di Fisica Nucleare, Sanitas EG and University of Padova) |
| 3.3. | Efficient Estimation of SEU effects in SRAM-based FPGAs, M. Sonza Reorda, L. Sterpone, M. Violante (Politecnico di Torino) |
| 15.00 - 15.15 | |
| 15.15 - 16.35 | Special Session 1: Robust Design Techniques for Soft Errors Organizer: C. Metra, University of Bologna Moderator: C. Metra, University of Bologna |
| S1.1. | Impact of Soft Error Challenge on SoC Design, Y. Zorian, V. Vardanian (Virage Logic) |
| S1.2. | DFT Assisted Built-In Soft Error Resilience, T.M. Mak, S. Mitra, M. Zhang (Intel Corporation) |
| S1.3. | Modeling Soft-Error Susceptibility for IP Blocks, R. Aitken, D. Bradley (ARM) |
| S1.4. | Trends and Tradeoffs in Designing Highly Robust Throughput Computing Oriented Chips and Servers, I. Parulkar, R. Cypher (Sun Microsystems) |
| 16.35 - 17.35 | Special Session 2: Simulation and Mitigation of Single Event Effects Organizer: L. Anghel, TIMA Laboratory Moderator: L. Anghel, TIMA Laboratory |
| S2.1. | Use of Nuclear Codes for Neutron Induced Nuclear Reactions in Microelectronics, Frédéric WROBEL (LPES-CRESA) |
| S2.2. | A Review of DASIE Family Code: Contribution to SEU/MBU Understanding, Guillaume Hubert et al. (EADS-CCR) |
| S2.3. | Mitigation Techniques for Single Event Effects, Michael Nicolaidis (iRoC Technologies) |
| 17.35 - 17.50 | |
| 17.50 - 18.50 | Special Session 3: Self Calibrating Design Organizer: K. Roy, Purdue University Moderator: |
| S3.1. | Does it Mean Less Testing for Self Calibrating Design ?, T.M. Mak (Intel Corporation) |
| S3.2. | Self Calibrating Circuit Design for Variation Tolerant VLSI Systems, Chris H. Kim (University of Minnesota), Steven Hsu, Ram Krishnamurthy, Shekhar Borkar (Intel Corporation), Kaushik Roy (Purdue University) |
| S3.3. | On-Chip Self-Calibration of RF Circuits Using Specification Based Built-In Self-Test (S-BIST), DongHoon Han, Sermet Akbay, Soumendu Bhattacharya, A. Chatterjee (Gerorgia Institute of Technology), William R. Eisenstadt (University of Florida) |
| 20.00 | Welcome Dinner |
| Thursday, July 7th, 2005 | |
| 08.30 - 09.50 | Special Session 4: Secure Implementation Organizer: R. Leveugle, TIMA Laboratory Moderator: R. Leveugle, TIMA Laboratory |
| S4.1. | Introduction to Fault Attacks on Smartcard, Antoine Lemarechal (Oberthur Card Systems) |
| S4.2. | Security Constraints in Integrated Circuits, Laurent Sourgen (STMicroelectronics) |
| S4.3. | Side-channel Issues for Designing Secure Hardware Implementations, Lejla Batina, Nele Mentens, Ingrid Verbauwhede (K.U.Leuven) |
| S4.4. | Security Testing for Hardware Products: the Security Evaluations Practice, Alain Merle, Jessy Clediere (CESTI LETI, CEA) |
| 09.50 - 10.50 | Session 4: On-Line Testing for Secure and Asynchronous Chips Moderators: E. Simeu, Tima Laboratory A. Pagni, STMicroelectronics |
| 4.1. | Hardening Techniques against Transient Faults for Asynchronous Circuits, Y. Monnet, M. Renaudin, R. Leveugle (TIMA Laboratory) |
| 4.2. | On-line Testing of Globally Asynchronous Circuits, D. Shang, A. Bystrov, A. Yakovlev, D. Koppad (University of Newcastle upon Tyne) |
| 4.3. | On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-box Implementations, V. Ocheretnij, G. Kouznetsov (University of Potsdam), R. Karri (Polytechnic University), M. Goessel (University of Potsdam) |
| 10.50 - 11.00 | |
| 11.00 - 12.00 | Session 5: Self Checking Strategies Moderator: R. Stefanelli, Politecnico di Milano |
| 5.1. | Fast, Parallel Two-Rail Code Checker with Enhanced Testability, S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, A. Efthymiou (University of Athens), (University of Ioannia), (Southern Illinois University) |
| 5.2. | Power-balanced Self Checking Circuits for Cryptographic Chips, J. Murphy, A. Bystrov, A. Yakovlev (University of Newcastle upon Tyne) |
| 5.3. | On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization, M. Omaña, O. Losco, C. Metra (University of Bologna), A. Pagni (STMicroelectronics) |
| 12.00 - 14.00 | Lunch |
| 14.00 - 15.00 | Session 6: Process Variations, Leakage and Power Supply Noise Detection and Tolerance Moderators: C. Landrault, LIRMM M. Pflanz, IBM |
| 6.1. | Process Variation Tolerant Online Current Monitor for Fault Immune Systems, Q. Chen, S. Mukhopadhyay, H. Mahmoodi, K. Roy (Purdue University) |
| 6.2. | A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits, B. Alorda, S. Bota, J. Segura (University de les Illes Balears) |
| 6.3. | Coding Techniques for Low Switching Noise in Fault Tolerant Busses, A.K. Nieuwland, A. Katoch (Philips Research Laboratories), D. Rossi, C. Metra (University of Bologna) |
| 15.00 - 15.40 | Session 7: Posters Moderator: S. Hellebrand, University of Innsbruck |
| 7.1. | Modeling of Transients Caused by a Laser Attack on Smart Cards, D. Leroy (iRoC Tecnologies), S.J. Piestrak, F. Monteiro, A. Dandache (University of Metz) |
| 7.2. | Scrubbing and Partitioning for Protection of Memory Systems, R. Mariani, G. Boschi (Yogitech SPA) |
| 7.3. | A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory, A. Krasniewski (Warsaw University of Technology) |
| 7.4. | Software Based Online Memory Test for Highly Available Systems, A. Singh, D. Bose (Sun Microsystems) |
| 7.5. | Design of a Self Checking Reed Solomon Encoder, G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano (University of Rome “Tor Vergata”) |
| 7.6. | Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores using Reconfigurable Hardware and Scan Shift, K. Katoh (Chiba University), A. Doumar (Alakhawayn University), H. Ito (Chiba University) |
| 7.7. | A 32-bit COTS-based Fault-Tolerant Embedded System, A. Rajabzadeh (Razi University) |
| 7.8. | On the Proposition of an EMI-Based Fault Injection, Fabian Vargas, Danniel L. Cavalcante, Edmundo Gatti*, Darcio Prestes, Daniel Lupi, Eduardo Rhod, (Catholic University and Instituto Nacional de Tecnologia Industrial) |
| 15.40 - 16.40 | Panel: On-Line Testing for Secure Implementations: Design and Validation Organizer: R. Leveugle, TIMA Laboratory Moderator: Y. Zorian, Virage Logic |
| Participants: |
L. Breveglieri, Politecnico di Milano, Italy R. Leveugle, TIMA Laboratory, France A. Nieuwland, Philips Research Labs., The Netherlands K. Rothbart, T.U. Graz, Austria J.P. Seifert, Intel Corporation, USA |
| 17.30 | Social Event, Tour and Gala Dinner |
| Friday, July 8th, 2005 | |
| 08.30 - 09.30 | Session 8: Testing Issues Moderators: B. Straube, Fraunhofer IIS/EAS I. Polian, Albert-Ludwigs-Univ. of Freiburg |
| 8.1. | Accumulator-based Weighted Pattern Generation, I. Voyiatzis, D. Gizopoulos, A. Paschalis (TEI of Athens, University of Piraeus and University of Athens) |
| 8.2. | A Hamming Distance Based Test Pattern Generator With Improved Fault Coverage, D.K. Pradhan (University of Bristol), D. Kagaris (Southern Illinois University) |
| 8.3. | Test Generation Methodology for High-Speed Floating Point Adders, G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis, (University of Piraeus and University of Athens) |
| 09.30 - 10.30 | Session 9: SoC Testing and Fault Tolerance Moderators: I. Levendel, Connectivities E. Bohel, Robert Bosch GmbH |
| 9.1. | Integrating BIST Techniques for On-line SoC Testing, A. Manzone, P.Bernardi, M.Grosso, M.Rebaudengo, E.Sanchez, M.Sonza Reorda (Centro Ricerche Fiat and Politecnico di Torino) |
| 9.2. | A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features, R. Kothe, C. Galke, H.T. Vierhaus (Brandenburg University of Technology) |
| 9.3. | On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors, M. Portolan, R. Leveugle (TIMA Laboratory) |
| 10.30 - 10.45 | |
| 10.45 - 11.45 | Session 10: Multiple Bit Upset Evaluation and Correction Moderator: H-J. Wunderlick, Stuttgard University R. Velazco, TIMA Laboratory |
| 10.1. | Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators, E. Schüler, L. Carro (Universidade Federal do Rio Grande do Sul) |
| 10.2. | A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations, R. Leveugle (TIMA Laboratory) |
| 10.3. | Radiation Induced Single-word Multiple-bit Upsets Correction in SRAM, B. Gill (Case Western Reserve University), M. Nicolaidis (iRoC Technologies), C. Papachristou (Case Western Reserve University) |
| 11.45 - 12.45 | Session 11: Timing, Yield, and Reliability Issues Moderator: A. Ivanov, University of Brit. Columbia |
| 11.1. | Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub-100nm Technology, A. Datta, S. Mukhopadhyay, S. Bhunia, K. Roy (Purdue University) |
| 11.2. | Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test, M. Rodriguez-Irago, J.J. Rodríguez Andina, F. Vargas, M.B. Santos, I.C Teixeira, J.P. Teixeira, (IST/INESC-ID, University of Vigo and PUCRS) |
| 11.3. | A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning, A. Raychowdhury, S. Ghosh, K. Roy (Purdue University) |
| 12.45 - 14.30 | Lunch |
| 14.00 - 15.00 | Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing Organizer: Y. Crouzet, LAAS-CNRS Moderator: J. Arlat, LAAS-CNRS |
| S5.1. | Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing, Y. Crouzet, J. Collet, J. Arlat (LAAS-CNRS) |
| S5.2. | Overview of Soft Errors Issues in Aerospace Systems, C. Boléat (Astrium EADS), G. Colas (Thales Avionics) |
| S5.3. | How to Characterize the Problem of SEU in Processors and Representative Errors Observed in Flight, R. Velazco (TIMA Laboratory), R. Ecoffet (CNES), F. Faure (TIMA Laboratory) |
| S5.4. | Evaluation of SET and SEU Effects at Multiple Abstraction Levels, L. Anghel, R. Leveugle, P. Vanhauwaert (TIMA Laboratory) |
| S5.5. | How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family, N. Renaud (ATMEL) |
| S5.6. | How to Cope with SEU/SET at System Level ?, M. Pignol (CNES) |
| S5.7. | Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future, A. Pouponnot, (ESA/ESTEC) |
| 16.50 - 17.00 | Closing
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