| 12th IEEE International On-Line Testing Symposium |  |
| Grand Hotel di Como - Lake of Como, Italy July 10-12, 2006. |
Technical Program |
| Monday July 10th, 2006 | |
| 07.30 - 08.30 | Registration |
| 08.30 - 08.45 | Welcome Message General Co-Chairs: C. Metra, M. Nicolaidis Program Co-Chairs: R. Aitken, R. Leveugle |
| 08.45 - 09.30 | Keynote Talk: “The challenge of reliability in future complex systems” Andrea Cuomo, STMicroelectronics Executive Vice-President |
| 09.30 - 10.00 | Invited Talk: “Extending Moore's Law into the next Decade - the SER Challenge” Norbert Seifert, Intel Corp. |
| 10.00 - 10.20 |  |
| 10.20 - 11.20 | Session 1: Fault effects and self-checking techniques Moderators: P. Ienne, EPFL L. Anghel, TIMA Laboratory |
| 1.1. | Characterizing Laser-Induced Pulses in ICs: Methodology and Results, D. Leroy (iRoC Technologies), S.J. Piestrak, F. Monteiro, A. Dandache (U. Metz), S. Rossignol (iRoC Technologies), P. Moitrel (Gemplus) |
| 1.2. | Path (Min) Delay Faults and Their Impact on Self-Checking Circuits’ Operation, C. Metra, M. Omaña, D. Rossi, J.M. Cazeaux (U. Bologna), T.M. Mak (Intel) |
| 1.3. | A New Self-Checking and Code-Disjoint Non-Restoring Array Divider, D. Marienfeld, E.S. Sogomonyan, V. Otcheretnij, M. Gössel (U. Potsdam) |
| 11.20 - 11.25 | Break |
| 11.25 - 12.25 | Session 2: BIST Techniques Moderators: S. Hellebrand, U. Innsbruck P. Girard, LIRMM |
| 2.1. | Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor, S. Ghosh, S. Bhunia, A. Raychowdhury, K. Roy (Purdue U.) |
| 2.2. | A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST, C. Yu, S.M. Reddy (U. Iowa) |
| 2.3. | Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding, S. Neophytou, M.K. Michael (U. Cyprus), S. Tragoudas (Southern Illinois U.) |
| 12.25 - 13.30 | Lunch |
| 13.30 - 14.30 | Session 3: Technology robustness Moderators: R. Velazco, TIMA Laboratory C. Metra, U. Bologna |
| 3.1. | Erratic Effects of Irradiation in Floating Gate Memory Cells, G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi (Padova U., INFN and STMicroelectronics) |
| 3.2. | Factors that impact the Critical Charge of Memory Elements, T. Heijmen (Philips Research), D. Giot, P. Roche (STMicroelectronics) |
| 3.3. | Prediction of Transient induced by Neutron/Proton in CMOS Combinational Logic Cells, G. Hubert, A. Bougerol, F. Miller, N. Buard, L. Anghel, T. Carriere, F. Wrobel, R.Gaillard (EADS, TIMA Laboratory, U. of Nice and INFODUC) |
| 14.30 - 14.35 | Break |
| 14.35 - 15.55 | Special Session 1: Memory Reliability Challenges Organizer: C. Metra, U. Bologna Moderators: H. J. Wunderlich, U. Stuttgart F. Salice, Politec. di Milano |
| S1.1. | Embedded Memory Reliability Trends and Solutions, Y. Zorian (Virage Logic) |
| S1.2. | Reliability Issues for Embedded SRAM at 90nm and Below, R. Aitken (ARM) |
| S1.3. | Testing Strategies for Non Volatile Memory Reliability, G. Crisenza (STMicroelectronics) |
| S1.4. | Towards the Methodology Of On-line Diagnosis, R. Rajsuman (Advantest) |
| 15.55 - 16.15 | |
| 16.15 - 17.35 | Special Session 2: Test and Reliability Challenges for Innovative Systems Organizer: C. Metra, U. Bologna Moderators: P. Prinetto, Politecnico di Torino J. Hayes, U. Michigan |
| S2.1. | Test Challenges for 3D Circuits, T.M. Mak (Intel Corporation) |
| S2.2. | Trends and Tradeoffs in Designing Highly Robust Throughput on Chip Communication Network, M. Coppola (STMicroelectronics) |
| S2.3. | Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs, M. Abadir (Freescale) |
| S2.4. | The Consequences of Variability in Software, I. Levendel (Levendel & Associates) |
| 17.35 - 17.40 | Break |
| 17.40 - 19.00 | Panel 1: From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately ? Organizers: L. Anghel, TIMA Laboratory N. Buard, EADS-CCR
Moderators: P. Heins, Airbus
T. Carriere, EADS-ST |
| Panelists |
D. Alexandrescu, IRoC Technologies L. Anghel, TIMA Laboratory S. Bota, U. Iles Baleares N. Buard, EADS-CCR C.Lopez, U. Carlos III Madrid A. Nieuwland, Philips N. Renaud, Atmel |
| 20.30 | Welcome Reception |
| Tuesday, July 11th, 2006 | |
| 08.30 - 09.30 | Embedded tutorials. Innovative Design for Robustness Moderators: B. Straube, Fraunhofer IIS/EAS A. Munoz, Intel Corp. |
| ET.1. | Fault Tolerance Implementation within SRAM Based FPGA Designs based upon the Increased Level of Single Event Upset Susceptibility, M. Berg (NASA) |
| ET.2. | Asynchronous Design and Fault Robustness, M. Renaudin (TIMA Laboratory) |
| 09.30 - 09.50 | |
| 09.50 - 10.50 | Session 4: Soft Errors and Latchup Mitigations Moderators: F. Lima Kastensmidt, UFRGS A. Rosti, STMicroelectronics |
| 4.1. | Combinational Logic Soft Error Analysis and Protection, A.K. Nieuwland, S. Jasarevic, G. Jerin (Philips Research, Philips Semiconductor, and Lund U.) |
| 4.2. | An Improved Technique for Reducing False Alarms Due to Soft Errors, S. Kundu (U. Massachusetts), I Polian (Albert-Ludwigs U.) |
| 4.3. | A Low-Cost Single-Event Latchup Mitigation Scheme, M. Nicolaidis (iRoC Technologies and TIMA Laboratory) |
| 10.50 - 11.00 | Break |
| 11.00 - 12.00 | Session 5: Secure circuits Moderators: L. Sourgen, STMicroelectronics R. Leveugle, TIMA Laboratory |
| 5.1. | Secure Scan Techniques: a Comparison, D. Hély, F. Bancel (STMicroelectronics), M.-L. Flottes, B. Rouzeyre (LIRMM) |
| 5.2. | Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor, Y. Monnet, M. Renaudin, R. Leveugle (TIMA Laboratory), N. Feyt, P. Moitrel, M'Buwa Nzengue (Gemplus) |
| 5.3. | Power Attacks on Secure Hardware Based on Early Propagation of Data, K.J. Kulikowski, M.G. Karpovsky, A. Taubin (Boston U.) |
| 12.00 - 13.30 | Lunch |
| 13.30 - 14.30 | Session 6: Fault detection techniques Moderators: M. Pflanz, IBM Germany S. Fanfoni, STMicroelectronics |
| 6.1. | Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs, M. Cassel dos Santos, F. Lima Kastensmidt (UFRGS) |
| 6.2. | On-line Fault Detection and Location for NoC Interconnects, C. Grecu, A. Ivanov, R. Saleh, E. Sogomonyan, P. Pande (U. British Columbia, U. Postdam, and Washington State U.) |
| 6.3. | CEDA: Control-flow Error Detection through Assertions, R. Vemu, J.A. Abraham (U. Texas) |
| 14.30 - 14.35 | Break |
| 14.35 - 15.15 | Session 7: Analog circuits dependability Moderators: E. Simeu, TIMA Laboratory R. Aitken, ARM |
| 7.1. | On-Line Error Detection in Wireless RF Transmitters using Real-Time Streaming Data, V. Natarajan, G. Srinivasan, A. Chatterjee (Georgia Institute of Technology) |
| 7.2. | Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study, C. Lazzari, L. Anghel, R. Reis (UFRGS and TIMA Laboratory) |
| 15.15 - 16.00 | Session 8: Posters Moderator: C. Landrault, LIRMM |
| 8.1. | Embedded Borden 2-UED Code Checkers, S. Tarnick (4TECH GmbH) |
| 8.2. | Error Detection in an RSA Architecture by means of Residue Codes, L. Breveglieri (Politecnico di Milano), I. Koren (U. Massachusetts), P. Maistri (Politecnico di Milano) |
| 8.3. | Localization of Faults in Radix-n Signed Digit Adders, G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano (U. Rome) |
| 8.4. | Embedded Scan Test with Diagnostic Features for Self-Testing SoCs, C. Galke, R. Kothe, J. Honko, K. Winkler, H.T. Vierhaus (U.T. Cottbus) |
| 8.5. | Emulation-based Fault Injection in Circuits with Embedded Memories, M. Garcia-Valderas, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena (U. Madrid) |
| 8.6. | Fault Tolerant System Design Method Based on Self-Checking Circuits, P. Kubalik, P. Fiser, H. Kubatova (CTU. Prague) |
| 8.7. | Built-in Self Repair by Reconfiguration of FPGAs, S. Habermann, R. Kothe, H.T. Vierhaus (U.T. Cottbus) |
| 8.8. | Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices, L. Sterpone, M. Violante (Politecnico di Torino) |
| 8.9. | Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers, A. Pereira Frantz, L. Carro, E. Cota, F. Lima Kastensmidt (UFRGS) |
| 8.10. | Diophantine-Equation Based Arithmetic Test Set Embedding, D. Nikolos, D. Kagaris, S. Gidaros (U. Patras) |
| 8.11. | Design of a Robust 8-Bit Microprocessor to Soft Single Event Effects, R. Possamai Bastos, F. Lima Kastensmidt, R. Reis (UFRGS) |
| 8.12. | Online Fault Detection, Diagnosis and Recovery Algorithms in RTL Domain, N. Karimi, S. Mirkhani, Z. Navabi (U. Tehran) |
| 16.00 - 17.00 | Panel 2: Should logic SER be solved at the circuit level ? Organizers: T.M. Mak, Intel Corp. S. Mitra, Stanford U.
Moderator: T.M. Mak, Intel Corp. |
| Panelists |
J. Abraham, U. Texas at Austin T. Austin, U. Michigan R. Iyer, U. Illinois at Urbana-Champaign S. Mitra, Stanford U. A. Wood, Sun |
| 17.30 | Social Event, Tour and Gala Dinner |
| Wednesday, July 12th, 2006 | |
| 08.30 - 09.30 | Session 9: Reliable systems Moderators: B.C. Paul, Stanford U. R. Negrini, Politec. di Milano |
| 9.1. | DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTS-based Spacecraft Supercomputers, M. Pignol (CNES) |
| 9.2. | Fault-robust microcontrollers for automotive applications, R. Mariani, P. Fuhrmann, B. Vittorelli (YOGITECH SpA, Philips Research, and ARM) |
| 9.3. | Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures, J. Collet, P. Zajac, Y. Crouzet, A. Napieralski (LAAS-CNRS and T.U. Lodz) |
| 09.30 - 09.50 | |
| 09.50 - 10.50 | Session 10: Dependability analysis Moderators: E. Boehl, Robert Bosch GmbH A. Galluzzo, STMicroelectronics |
| 10.1. | Hardware-in-the-loop-based Dependability Analysis of Automotive Systems, M. Sonza Reorda, M. Violante (Politecnico di Torino) |
| 10.2. | A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs, P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis (U. Athens and U. Piraeus) |
| 10.3. | Real Time Fault Injection Using a Modified Debugging Infrastructure, A.V. Fidalgo, G.R. Alves, J.M. Ferreira (ISEP) |
| 10.50 - 11.00 | Break |
| 11.00 - 12.00 | Session 11: New topics in fault detection Moderators: M. Rebaudengo, Politec. di Torino R. Stefanelli, Politec. di Milano |
| 11.1. | The Problem of On-Line Testing Methods in Approximate Data Processing, A. Drozd, M. Lobachev, J. Drozd (Odessa National Polytechnic U.) |
| 11.2. | Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes, M. Rodriguez-Irago, J.J. Rodriguez Andina, F. Vargas, J. Semiao, I.C. Teixeira, J.P. Teixeira (IST / INESC-ID, U. Vigo, and PUCRS) |
| 11.3. | Online testing by protocol decomposition, D. Koppad, D. Sokolov, A. Bystrov, A. Yakovlev (U. Newcastle) |
| 12.00 - 13.30 | Lunch |
| 13.30 - 14.30 | Panel 3: Reliability in Automotive Organizer: A. Pagni, STMicroelectronics Moderator: D. Appello, STMicroelectronics |
| Panelists |
M. Abate, Magneti Marelli Powertrain R. Mariani, YOGITECH SPA L. Valsecchi, STMicroelectronics |
| 14.30 - 14.35 | Break |
| 14.35 - 15.15 | Special Session 3: SER Trends: Vision and Developments from European IDMs Organizer: M. Nicolaidis, TIMA Laboratory Moderator: M. Nicolaidis, TIMA Laboratory |
| S3.1. | Soft Error Rates in Deep-Submicron CMOS Technologies, T. Heijmen (Philips Research) |
| S3.2. | Trend of DRAM Soft Errors, G. Schindlbeck (Infineon) |
| 15.15 - 15.20 | Break |
| 15.20 - 16.20 | Session 12: Checkers and error correction Moderators: Y. Tsiatouhas, U. Ioannina P. Gloesekoetter, Intel Corp. |
| 12.1. | Checker No-Harm Alarm Robustness, D. Rossi, M. Omana, C. Metra, A. Pagni (U. Bologna) |
| 12.2. | Designing Robust Checkers in the Presence of Massive Timing Errors, F. Worm, P. Thiran, P. Ienne (EPFL) |
| 12.3. | Error Correction in Arithmetic Operations by I/O Inversion, P. Oikonomakos, P. Fox (U. Cambridge) |
| 16.20 - 16.30 | Closing
 |
©2006 Laboratoire TIMA.
Tous droits réservés. |