Keynote Talks

Soft-errors phenomenon impacts on Design For Reliability technologies 
Marc Derbey, President and CEO iRoC Technologies

Monday, July 9, 2007

Abstract:
We will mainly address here the “alter ego” of quality, which is reliability, and is becoming a growing concern for designers using the latest technologies. After the DFM nodes in 90nm and 65nm, we are entering the DFR area, or Design For Reliability straddling from 65nm to 45nm and beyond. Because of the randomness character of reliability - failures can happen anytime anywhere - executives should mitigate reliability problems in terms of risk, which costs include cost of recalls, warranty costs, and loss of goodwill.

Taking as an example the soft error phenomenon, we demonstrate how the industry first started to respond to this new technology scaling problem with silicon test to measure and understand the issue, but should quickly move to resolving reliability issues early in the design. In this field, designers can largely benefit from new EDA analysis tools and specific IPs to overcome in a timely and economical manner this new hurdle.

Presenter’s biography:
Marc Derbey was appointed CEO of iRoC Technologies in March 2006. Previously, he served as General Manager for European Operations where he managed all engineering efforts for both Operations and R&D. Marc sees his new position as CEO as a challenge to improve operating efficiency and build a strong team with both technical and commercial abilities. Marc has over 15 years experience in the software industry, managing service and software development teams for various multinational companies. He came to iRoC Technologies from Sun Microsystems where he was in charge of the Telco high availability software product development team. Prior to Sun Microsystems, Marc was senior manager at Bull SA where he was in charge of telecom software developments, and AIX kernel developments for NUMA technology. Marc holds a B.S in Computer Science for the Joseph Fourier University of Grenoble, an M.S in Artificial Intelligence from the Paul Sabatier University of Toulouse, and is certified from the Program Management Institute.

Blurring the Layers of Abstractions: Time to take a step back?
Krisztián Flautner, Director of Research and Development, ARM Ltd

Tuesday, July 10, 2007

Abstract:
Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features. This talk will describe some of the recent work at ARM on designing architectures which dynamically optimize operating parameters for temporal conditions.

Speaker’s Biography
Krisztián Flautner is the director of research and development at ARM Ltd. His research interests include high-performance, energy efficient processing platforms and advanced software environments. Flautner received a PhD in computer science and engineering from the University of Michigan. He is a member of the ACM and the IEEE.

Invited Talk

Accelerating Yield Ramp through Real-Time Testing
Sanjiv Taneja, Vice President and General Manager of Test Technology, Cadence

Monday, July 9, 2007

Abstract:
With the increasing need for design specific yield optimization in nanometer technologies, it is becoming increasingly important to accelerate the identification of the root cause of systematic defects under very tight test cost constraints. This talk will give a high level overview of addressing these demanding challenges  through a mix of cross-disciplinary EDA technologies spanning scan diagnostics, DFT, ATPG, BIST, DFM and real-time monitoring from ATE systems

Speaker’s Biography
Mr. Sanjiv Taneja is the Vice President and General Manager of the Encounter Test business unit at Cadence Design Systems. Mr. Taneja joined Cadence in October 1998 as part of the acquisition of Bell Labs Design Automation and has served in a variety of roles including product marketing, business development, strategic alliances and operations. Mr. Taneja started his career at Bell Labs where he spent over 13 years in EDA software development, engineering management and strategic alliances. Mr. Taneja holds a BS degree in Electrical Engineering from Indian IIT Delhi, MS degree in Computer Science from Ohio State University, and MBA from New York University.