Final Technical Program
Sunday July 8 2007
08:00 – 09:00 Tutorial Registration
09:00 – 17:00 Test Technology Educational Program (TTEP) 2007 Full-Day Tutorial
Soft Errors: Technology Trends, System Effects and Production Techniques
S.Mitra (Stanford University)
P.Sanda (IBM)
N.Seifert (Intel)
(breaks: 10:30-11:00 and 15:00-15:30, lunch: 12:30-13:30)
16:00 – 18:00 Symposium Registration
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Monday July 9 2007
07:30 – 09:00 Symposium Registration
09:00 – 10:30 Opening Session
09:00 – 09:15 Welcome Message
M.Nicolaidis (TIMA Laboratory)
A.Paschalis (University of Athens)
General Co-Chairs
D.Gizopoulos (University of Piraeus)
TM Mak (Intel)
Program Co-Chairs
Keynote/Invited Talks Introduction
Yervant Zorian (VirageLogic)
09:15 – 10:00 Keynote Talk
Soft-errors phenomenon impacts on Design For Reliability technologies
Marc Derbey, President and CEO (iRoC Technologies)
10:00 – 10:30 Invited Talk
Accelerating Yield Ramp through Real-Time Testing
Sanjiv Taneja, Vice President and General Manager of Test Technology (Cadence)
10:30 – 10:40 Break
10:40 – 11:40 Session 1: Reliability Issues in Nanometer Technologies
Moderators
M.Abadir (Freescale)
C.Landrault (LIRMM)
1.1 Fuse: A Technique to Anticipate Failures due to Degradation in ALUs,
J.Abella, X.Vera, O.Unsal, O.Ergin, A.Gonzalez, (Intel Barcelona Research Center,
Barcelona Supercomputing Center and TOBB University of Economics and Technology)
1.2 Design for Resilience to Soft Errors and Variations, M.Zhang, TM Mak, J.Tschanz, K.S.Kim, N.Seifert,
D.Lu (Intel)
1.3 Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield, S.Paul,
R.S.Chakraborty, S.Bhunia (Case Western Reserve University)
11:40 – 12:00 Coffee Break
12:00 – 13:00 Session 2: Network-on-Chip Reliability and Fault Tolerance
Moderators
S.Mitra (Stanford University)
J.P.Teixeira (IST/INESC-ID)
2.1 Essential Fault-Tolerance Metrics for NoC Infrastructures, C.Grecu, L.Anghel, P.Pande, A.Ivanov,
R.Saleh (University of British Columbia, TIMA Laboratory and Washington State University)
2.2 Configurable Error Control Scheme for NoC Signal Integrity,
D.Rossi, P.Angelini, C.Metra (University of Bologna)
2.3 An Analytical Model for Reliability Evaluation of NoC Architectures, A.Dalirsani, M.Hosseinabady,
Z.Navabi (University of Tehran and Northeastern University)
13:00 – 14:00 Lunch
14:00 – 15:00 Session 3: Secure Systems
Moderators
E.Boehl (Robert Bosch GmbH)
M.Michael (University of Cyprus)
3.1 An On-Line Fault Detection Scheme for SBoxes in Secure Circuits,
G.Di Natale, M.-L.Flottes, B.Rouzeyre (LIRMM)
3.2 Latchup effect in CMOS IC: a Solution for Crypto-Processors Protection against Fault Injection Attacks?,
N.Buard, F.Miller, C.Ruby, R.Gaillard (EADS and INFODUC)
3.3 An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding,O.B.Khaleel, C.A.Papachristou,
F.Wolff, K.Pekmestzi (Case Western Reserve University and National Technical University of Athens)
15:00 – 15:10 Break
15:10 – 16:10 Session 4: Large Scale Dependability
Moderators
C.Papachristou (Case Western Reserve University)
B.Straube (Fraunhofer IIS/EAS)
4.1 Online Monitoring of FPGA-based Co-Processing Engines Embedded in Dependable Workstations,
N.Bartzoudis, K.McDonald-Maier (University of Essex)
4.2 Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant
Spacecraft Supercomputers, M.Pignol (CNES)
4.3 Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs,
F.Vargas, L.Piccoli, J.Benfica, A.A. de Alecrim Jr., M.Moraes (Catholic University – PUCRS)
16:10 – 16:30 Coffee Break
16:30 – 17:30 Session 5: Dependability of Processors, SoCs and Asynchronous Circuits
Moderators
T.Heijmen (NXP Semiconductors)
M.Benabdenbi (University of Paris 6)
5.1 A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors,
M.Portela-Garcia, C.Lopez-Ongil, M.Garcia Valderas, L.Entrena (Universidad Carlos III de Madrid)
5.2 A Hybrid Approach to Fault Detection and Correction in SoCs, P.Bernardi, L.M.Veiras Bolzani,
M.Sonza Reorda (Politecnico di Torino)
5.3 Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs, Y.Monnet,
M.Renaudin, R.Leveugle (TIMA Laboratory)
17:30 – 17:45 Break
17:45 – 18:45 Special Session 1: Aging and Wearout Issues and Mitigation Approaches
Organizers:
Pia Sanda (IBM)
TM Mak (Intel)
Moderator
P.Sanda (IBM)
S1.1 Reliability issues in deep deep sub-micron technologies: time-dependent variability and its
impact on embedded system design,
Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor (IMEC)
S1.2 Infant Mortality -- the lesser known reliability issue, TM Mak (Intel)
S1.3 Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout,
Subhasish Mitra (Stanford University)
20:00 Welcome Reception
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08:45 – 09:30 Keynote Talk
Moderator
C.Metra (University of Bologna)
Blurring the Layers of Abstractions:Time to take a step back?
Krisztián Flautner, Director of Research and Development (ARM Ltd)
09:30 – 09:40 Break
09:40 – 11:00 Session 6: Radiation Effects
Moderators
R.Velazco (TIMA)
N.Seifert (Intel)
6.1 Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs,
T.Heijmen (NXP Semiconductors)
6.2 Multiple Event Transients Induced by Nuclear Reactions in CMOS Logic Cells,
C.Rusu, A.Bougerol, L.Anghel, C.Weulerse, N.Buard, S.Benhammadi, N.Renaud,
G.Hubert, F.Wrobel, T.Carriere, R.Gaillard (TIMA Laboratory, EADS, ATMEL, LPES-CRESA,
University of Nice-Sophia Antipolis and INFODUC)
6.3 Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions,
M.Bagatin, G.Cellere, S.Gerardin, A.Paccagnella, A.Visconti, S.Beltrami, M.Maccarrone
(Padova University and STMicroelectronics)
6.4 On Derating Soft Error Probability Based on Strength Filtering, A.Sanyal,
S.Kundu (University of Massachusetts, Amherst)
11:00 – 11:20 Coffee Break
11:20 – 12:20 Session 7: Signal Integrity and Error Compensation
Moderators
N.Buard (EADS)
A.Bystrov (University of Newcastle upon Tyne)
7.1 Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics,
P.Pande, A.Ganguly, B.Feero, C.Grecu (Washington State University and University of British Columbia)
7.2 On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits, J.Semião, J.Freijedo,
J.J.Rodríguez-Andina, F.Vargas, M.B.Santos, I.C.Teixeira and J.P.Teixeira (IST/INESC-ID Lisboa,
University of Algarve, PUCRS and University of Vigo)
7.3 Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums,
M.Nisar, M.Ashouei, A.Chatterjee (Georgia Institute of Technology)
12:20 – 13:30 Lunch
13:30 – 14:30 Special Session 2 – Panel: SER Trends in 45nm and Beyond
Organizers:
Lorena Anghel (TIMA)
Dimitris Gizopoulos (University of Piraeus)
Moderator
Lorena Anghel (TIMA)
Panelists:
Tino Heijmen (NXP)
Franz Ruckerbauer (Infineon)
Norbert Seifert (Intel)
Marc Derbey (iRoC)
Pia Sanda (IBM)
Yervant Zorian (VirageLogic)
Eberhard Boehl (Robert Bosch GmbH)
14:30 – 15:30 Session 8: Posters
Moderator
N.Kranitis (University of Athens)
8.1 Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment,
X.Cano, S.Bota, R.Graciani, D.Gascón, A.Herms, A.Comerma, J.Segura, L.Garrido
(Universitat de Barcelona and Universitat de les Illes Balears)
8.2 Robustness of circuits under delay-induced faults: test of AES with the PAFI tool, O.Faurax,
A.Tria, L.Freund, F.Bancel (Ecole des Mines de St´Etienne, CEA-LETI, STMicroelectronics
and Universite de la Mediterranee)
8.3 A systematic approach for Failure Modes and Effects Analysis of System-On-Chips, R.Mariani,
G.Boschi (Yogitech)
8.4 Highly Reliable Power Aware Memory Design, C.A.Argyrides, D.K.Pradhan (University of Bristol)
8.5 Accelerating Soft Error Rate Testing through Pattern Selection, A.Sanyal, K.Ganeshpure,
S.Kundu (University of Massachusetts at Amherst)
8.6 Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders,
S.Pontarelli, L.Sterpone, G.C.Cardarilli, M.Re, M.Sonza Reorda, A.Salsano, M.Violante
(Universita di Roma ”Tor Vergata” and Politecnico di Torino)
8.7 Embedding test patterns into Low-Power BIST sequences,
I.Voyiatzis (Technological Educational Institute of Athens)
8.8 Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic
Block Codes, F.Monteiro, S.Piestrak, H.Jaber, A.Dandache (University of Metz)
8.9 Identification of Critical Errors in Imaging Applications,
I.Polian, D.Nowroth, B.Becker (Albert-Ludwigs University, Freiburg)
8.10 Soft Error Rates in 65 nm SRAMs – Analysis of new Phenomena, F.X.Ruckerbauer, Georg Georgakos (Infineon)
8.11 Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC,
M.Hosseinabady, M.H.Neishaburi, Z.Navabi , A.Benso, S.Di Carlo, P.Prinetto, G.Di Natale
(University of Tehran, Politecnico di Torino and LIRMM)
8.12 Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set, J.Mathew, H.Rahaman,
D.K.Pradhan (University of Bristol)
16:00 Social Event (Tour and Gala Dinner)
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Wednesday July 11 2007
09:00 – 10:00 Special Session 3: Fault-tolerant and Self-Adapting Design to Mitigate Power, Yield and Reliability
Issues in Upcoming Process Nodes
Organizer/Moderator
Rob Aitken (ARM)
S3.1 Statistical device variability and its impact on yield and performance, Asen Asenov (University of Glasgow)
S3.2 Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies,
Davide Pandini (ST Microelectronics)
S3.3 GRAAL: a fault tolerant architecture for enabling nanometric technologies, Michael Nicolaidis, TIMA
10:00 – 10:10 Break
10:10 – 11:10 Session 9: Fault Tolerance
Moderators
A.Salsano (Universita di Roma ”Tor Vergata”)
S.Kundu (University of Massachusetts, Amherst)
9.1 Automated Derivation of Application-aware Error Detectors Using Static Analysis,
K.Pattabiraman, Z.Kalbarczyk, R.K.Iyer (University of Illinois, Urbana)
9.2 On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs, M.G.Gericota,
L.F.Lemos, G.R.Alves, J.M.Ferreira (LABORIS/ISEP and FEUP)
9.3 A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits,
K.T.Gardiner, A.Yakovlev, A.Bystrov (University of Newcastle upon Tyne)
11:10 – 11:30 Coffee Break
11:30 – 12:30 Session 10: On-Line Testing for Analog, Mixed-Signal, RF and Delay Defect Tolerance
Moderators
P.Fouillat (IMS Bordeaux)
H.Stratigopoulos (TIMA)
10.1 Novel Process and Temperature-Stable, BICS for Embedded Analog and Mixed-Signal Test,
J.Liobe, M.Margala (University of Rochester and University of Massachusetts Lowell)
10.2 Envelop Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches, E.Simeu,
S.Mir, R.Kherreddine, H.N.Nguyen (TIMA Laboratory)
10.3 Tolerance to Small Delay Defects by Adaptive Clock Stretching, S.Ghosh, P.Ndai, S.Bhunia,
K.Roy (Purdue University and Case Western Reserve University)
12:30 – 13:30 Lunch
13:30 – 14:30 Special Session 4: Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips
Organizer/Moderator
Nacer-Eddine Zergainoh (TIMA)
S4.1 Resilience, ProductionYieldandSelf-Configuration in the Future Massively Defective Nanochips,
Jacques Henri Collet and Piotr Zając (LAAS)
S4.2 Surviving to Errors in Multi-Core Environments, Xavier Vera and Jaume Abella,
(Intel Barcelona Research Center)
S4.3 Architectural Trade-offs for Fault Tolerant Multi-Core Systems, Kris Flautner (ARM)
14:30 – 14:40 Break
14:40 – 15:40 Session 11: Processor-Based Testing
Moderators
A.Veneris (University of Toronto)
R.Iyer (University of Illinois, Urbana)
11.1 An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores, L.Bolzani,
E.Sanchez, M.Schillaci, M.Sonza Reorda, G.Squillero (Politecnico di Torino)
11.2 A Functional Self-Test Approach for Peripheral Cores in Processor-based SoCs, A.Apostolakis,
M.Psarakis, D.Gizopoulos, A.Paschalis (University of Piraeus and University of Athens)
11.3 A Configurable Modular Test Processor and Scan Controller Architecture, R.Frost, D.Rudolph, C.Galke,
R.Kothe, H.T.Vierhaus (Brandenburg University of Technology Cottbus)
15:40 – 16:00 Coffee Break
16:00 – 16:40 Session 12: Self-Checking and Self-Testing
Moderators
D.Pradhan (University of Bristol)
V.Pouget (IMS Bordeaux)
12.1 Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters, S.Tarnick (4TECH GmbH)
12.2 LFSR Reseeding with Irreducible Polynomials, S.Udar, D.Kagaris (Southern Illinois University)
16:40 – 17:00 Closing Remarks
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