Parameter Variations and Self-Calibration/Self-Repair Solutions
in Nanometer Technologies

Intended Audience | Tutorial Summary | Keywords | Program | Tutorial Organization |

Intended Audience:
This tutorial is targeted towards practicing test engineers, tool developers, researchers and students working on variability issues, yield and reliability improvement techniques for logic circuits and memory. [back to top]

Tutorial Summary:
Device level parameter variations caused by process imperfections,environmental variations (e.g. temperature) and aging effects (e.g. NBTI, HCI) manifest as variations in delay, leakage and noise margin in logic and memory circuits leading to manufacturing yield loss and reliability degradation. In this tutorial, we focus on post-silicon on-chip self-calibration and self-repair schemes for logic and memory circuits that can that can improve parametric yield and reliability. This tutorial will discuss causes of parametric variations and aging effects; present efficient techniques on-chip and on-line sensing and characterization of manufacturing variations and aging effects in device and circuit parameters; discuss circuit and system level techniques for selfcalibration and self-repair of logic and memory circuits; and explore selfrepairing systems for mixed signal design. The audience will be introduced to the post-silicon strategies for self-calibration and self-repair that constitutes a promising class of solutions to address variation induced parametric failures and associated test challenges. [back to top]

Keywords:
Variation-Tolerant Design, Process Monitoring Circuits, Speed Binning, Self-Calibration, Process Compensation, Self-Healing Circuits, Self-Repairing SRAM, Temperature-Aware Design. [back to top]

Program:
Device level parameter variations caused by process imperfections, environmental variations (e.g. temperature) and aging effects (e.g. NBTI, HCI) primarily manifest as variations in delay, leakage and noise margin in logic and memory circuits leading to manufacturing yield loss and reliability degradation. Post-silicon strategies for self-calibration and self-repair constitute a promising class of solutions to address power and variation induced parametric failures and associated test challenges. In this tutorial, we focus on on-chip calibration and repair schemes for logic and memory circuits that can improve parametric yield. The causes of parametric variations will be presented explaining their interaction with manufacturing process and intrinsic device physics. Efficient techniques on-chip and on-line sensing and characterization of device (e.g. threshold voltage) and circuit parameters (e.g. delay, leakage, noise-margin) will be discussed. Characterization methods for manufacturing variations as well as time-dependent degradations will be presented. The circuit and system level techniques for self-calibration and self-repair of logic and memory circuits will be introduced. Techniques that address die-to-die parameter variations will be discussed with emphasis on adaptive voltage and body-biasing. Design and test of SRAM that can repair itself and reduce the number of parametric failures will be presented. The tutorial will discuss techniques for online adaptation leading to reliability improvement under temperature fluctuations and device degradations. Finally, self-repairing systems for mixed signal design will be discussed. [back to top]

Tutorial Organization:

1. Introduction and Motivation (50 mn)
   1.a - Parameter variations due to process imperfection and intrinsic fluctuations
   1.b - Device degradation mechanisms (NBTI, HCI) and associated parameter variations
   1.c - Effect of temperature
   1.d - Delay and leakage variations
   1.e - Variation induced failures in memory
   1.f - Parametric yield analysis
   
2. Variation monitoring and Characterization Circuits (60 mn)
   2.a - Characterization of device parameters – threshold voltage
   2.b - Characterization of circuit parameters
   2.b.1 - Delay
   2.b.2 - Leakage
   2.b.3 - SRAM noise margin
   2.c - Device degradation monitoring and characterization - NBTI and PBTI
   2.d - Thermal characterization
   
3. Self-Calibration/Self-Repair in Logic (70 mn)
   3.a - Frequency calibration approaches and impact on speed binning
   3.b - Post-silicon process adaptation in static CMOS circuits
   3.b.1. - voltage scaling and clock stretching
   3.b.2. - body biasing
   3.c - Process compensation in dynamic circuits
   3.d - Self-repair against temperature and time-dependent degradation such as NBTI
   
4. Self-Repairing in SRAM (70 mn)
   4.a - Variation tolerant SRAM design solution
   4.b - Post-silicon self-repair in SRAM
   4.b.1. - Challenges to post-silicon repair in SRAM
   4.b.2. - Philosophy for self-repair in SRAM
   4.c - Design and measurement of self-repairing SRAM
   
5. Self-adaptation in Mixed-Signal SoC (50 mn)
   5.a - Variation impact on mixed-signal cores
   5.b - Process compensation in data converters and PLL
   5.c - Process compensation in DSP cores
   5.d - System-level healing
   
6. Conclusion and Discussion (30 mn)
   6.a - Current industrial practices
   6.b - Scaling trend and effectiveness of self-calibration/repair in future technologies
   6.c - Future research directions
   [back to top]