Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain
July 2-4, 2018
FEDfRO and IOLTS 2018 Keynotes
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Emerging Discontinuities in Design and Verification Methodologies
FEDFRO Keynote Talk: Monday July 2nd, 2018 08:45 – 09:30
Productive changes in electronic design and verification are usually incremental and can be adopted without disrupting the traditional design flow. Periodically, however, we reach a point where further improvements require disruptive change. Moving to a higher level of abstraction is one example. Dr. Rhines will discuss some of the emerging discontinuities that are making their way into the mainstream and project their future evolution.
WALDEN C. RHINES
President and Chief Executive Officer
Mentor, a Siemens Business
WALDEN C. RHINES is President and Chief Executive Officer of Mentor, a Siemens business. He was previously CEO of Mentor Graphics for 23 years and Chairman of the Board for 17 years. During his tenure at Mentor, revenue nearly quadrupled and market value of the company increased 10X.
Prior to joining Mentor Graphics, Dr. Rhines was Executive Vice President of Texas Instruments’ Semiconductor Group. During his 21 years at TI, he was President of the Data Systems Group and held numerous other semiconductor executive management positions.
Dr. Rhines has served on the boards of Cirrus Logic, QORVO, TriQuint Semiconductor, Global Logic and as Chairman of the Electronic Design Automation Consortium (five two-year terms) and is currently a director. He is also a board member of the Semiconductor Research Corporation and First Growth Children & Family Charities. He is a Lifetime Fellow of the IEEE and has served on the Board of Trustees of Lewis and Clark College, the National Advisory Board of the University of Michigan and Industrial Committees advising Stanford University and the University of Florida.
Dr. Rhines holds a Bachelor of Science degree in engineering from the University of Michigan, a Master of Science and PhD in materials science and engineering from Stanford University, a master of Business Administration from Southern Methodist University and Honorary Doctor of Technology degrees from the University of Florida and Nottingham Trent University.
Rethinking Memory System Design: Robustness, Energy, Performance
IOLTS Keynote: Tuesday July 3rd, 2018 12:30 – 13:15
The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy efficiency, performance, and reliability significantly more costly with conventional techniques. In fact, recent reliability issues with DRAM, such as the RowHammer problem, are already threatening system security and predictability. We are at the challenging intersection where issues in memory reliability and performance are tightly coupled with not only system cost and energy efficiency but also system security.
In this talk, we first discuss major challenges facing modern memory systems (and the computing platforms we currently design around the memory system) in the presence of greatly increasing demand for data and its fast analysis. We then examine some promising research and design directions to overcome these challenges. We discuss at least three key topics: 1) novel issues in memory reliability and security and how to enable fundamentally secure, reliable, safe architectures, 2) reducing memory latency and energy consumption by tackling the fixed-latency/energy mindset, 3) enabling data-centric and hence fundamentally energy-efficient architectures that are capable of performing computation near data. We will describe tradeoffs between latency-reliability-energy-security and how one can make the best of such tradeoffs in modern DRAM chips, based on our detailed experimental analyses of thousands of DRAM devices over the course of past 7 years. We will also touch briefly on robustness issues in planar and 3D NAND flash memories.
Prof. Onur Mutlu from ETH Zurich
Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the William D. and Nancy W. Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, and bioinformatics. He is especially interested in interactions across domains and between applications, system software, compilers, and microarchitecture, with a major current focus on memory and storage systems. A variety of techniques he, along with his group and collaborators, have invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS
in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. His industrial experience spans starting the Computer Architecture Group at Microsoft Research (2006-2009), and various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, faculty partnership awards from various companies, a healthy number of best paper or "Top Pick" paper recognitions at various computer systems and architecture venues, and the ACM Fellow recognition "for contributions to computer architecture
research, especially in memory systems." His computer architecture course lectures and materials are freely available on YouTube, and his research group makes software artifacts freely available online. For more information, please see his webpage at http://people.inf.ethz.ch/omutlu/.
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