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Application-Driven Target Setting, Fault Impact and High-Performance Computing and Machine Learning Resiliency<\/h2>\n\n\n\nSpeaker: Michael Paulitsch (Intel)<\/h4>\n\n\n\nSeptember 12th, 2022- 9:00 am – 10:00 am CET <\/h5>\n\n\n\n
Abstract:<\/strong> \u00a0Chip area is growing significantly in the next years, pushing requirements to detect and tolerate faults to new levels. Setting resiliency targets during chip design is essential in such an environment. We present different metrics for machine learning (ML) networks in such an environment and an accelerator-focused fault impact analysis. We apply this fault impact analysis framework to typical ML and High-Performance Computing applications and present impact analysis benefits. Furthermore, we present automated resiliency approaches at different levels (hardware, software, application). E.g. we show the effectiveness of application-level monitors in such environments. We also speculate on needed research.<\/p>\n\n\n\nShort bio:<\/strong> brings 20 years of work in theoretical and applied research and technology. He worked at university and in different industries (aerospace, railway, automotive) in dependability in safety-critical and real-time systems, including security aspects of all types.
Michael has been filling the role of a Dependability Systems Architect (Principal Engineer) at Intel, Munich, Germany, as part of Intel Labs since 2018. He pursues Dependable Artificial Intelligence and Machine Learning systems (resiliency) evaluation and ensures safe and dependable use of neural network models in safety-critical systems. The focus is on platform faults and the impact of accelerator technology on ML\/AI networks as well as High-Performance Applications. He also looks at novel safety monitoring approaches at different system levels (chip, platform, application) for safety-related topics for autonomous systems.<\/em><\/p>\n<\/div><\/div>\n\n\n\n