{"id":1950,"date":"2025-06-17T19:25:13","date_gmt":"2025-06-17T17:25:13","guid":{"rendered":"https:\/\/orion.polito.it\/iolts\/?page_id=1950"},"modified":"2025-07-07T15:35:39","modified_gmt":"2025-07-07T13:35:39","slug":"technical-program","status":"publish","type":"page","link":"https:\/\/orion.polito.it\/iolts\/technical-program\/","title":{"rendered":"Technical Program"},"content":{"rendered":"\n<p><em>All sessions are scheduled according to the <strong>local time<\/strong><\/em>.<\/p>\n\n\n\n<style>\n    table {\n        border-collapse: collapse;\n        width: 100%;\n    }\n\n    th,\n    td {\n        text-align: center;\n        padding: 1em;\n    }\n\n    th {\n        background-color: #F2E7FE;\n        color: #000000;\n    }\n\n    .keynote {\n        background-color: #6495ED;\n        color: #000000;\n    }\n    .closing {\n        background-color: #e99a9b;\n        color: #000000;\n    }\n\n    .registration {\n        background-color: #B2DFDB;\n        color: #000000;\n    }\n\n    .regular {\n        background-color: #adce96;\n        color: #000000;\n    }\n\n    .poster {\n        background-color: #C5CAE9;\n        color: #000000;\n    }\n\n    .special {\n        background-color: #FFCCBC;\n        color: #000000;\n    }\n\n    .social {\n        background-color: #E6EE9C;\n        color: #000000;\n    }\n\n    .welcome {\n        background-color: #E6EE9C;\n        color: #000000;\n    }\n\n    .opening {\n        background-color: #E6EE9C;\n        color: #000000;\n    }\n\n    .lunch {\n        background-color: #FFE0B2;\n        color: #000000;\n    }\n\n    .break {\n        background-color: #F5F5F5;\n        color: #000000;\n    }\n\n    .coffee {\n        background-color: #F5F5F5;\n        color: #000000;\n    }\n\n    .border-forced {\n        border: 1px solid #000;\n    }\n<\/style>\n\n<table dir=\"ltr\" border=\"1\" cellspacing=\"0\" cellpadding=\"0\" data-sheets-root=\"1\" data-sheets-baot=\"1\"><colgroup><col width=\"0\" \/><col width=\"200\" \/><col width=\"200\" \/><col width=\"200\" \/><\/colgroup>\n<tbody>\n<tr>\n<th>Timeslot<\/th>\n<th>July 7<\/th>\n<th>July 8<\/th>\n<th>July 9<\/th>\n<\/tr>\n<tr>\n<td>8:00 &#8211; 8:30<\/td>\n<td class=\"registration\" colspan=\"1\" rowspan=\"2\">\n<div>Registration &amp; Welcome Desk<\/div>\n<\/td>\n<td>&nbsp;<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>8:30 &#8211; 8:45<\/td>\n<td>&nbsp;<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>8:45 &#8211; 9:00<\/td>\n<td class=\"opening\">Opening Session<\/td>\n<td class=\"registration\" colspan=\"1\" rowspan=\"1\">\n<div>Registration &amp; Welcome Desk<\/div>\n<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>9:00 &#8211; 9:30<\/td>\n<td class=\"keynote\" colspan=\"1\" rowspan=\"2\">\n<div><a href=\"#k1\">Keynote 1<\/a><\/div>\n<\/td>\n<td class=\"keynote\" colspan=\"1\" rowspan=\"2\">\n<div><a href=\"#k2\">Keynote 2<\/a><\/div>\n<\/td>\n<td class=\"registration\">\n<div>\n<div>Registration &amp; Welcome Desk<\/div>\n<\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>9:30 &#8211; 10:00<\/td>\n<td class=\"regular\" colspan=\"1\" rowspan=\"2\">\n<div><a href=\"#rs5\">Regular Session 5<\/a><\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>10:00 &#8211; 10:30<\/td>\n<td class=\"coffee\"><i class=\"fas fa-mug-hot\"><\/i> Coffee Break<\/td>\n<td class=\"coffee\"><i class=\"fas fa-mug-hot\"><\/i> Coffee Break<\/td>\n<\/tr>\n<tr>\n<td>10:30 &#8211; 11:30<\/td>\n<td class=\"regular\"><a href=\"#rs1\">Regular Session 1<\/a><\/td>\n<td class=\"special\"><a href=\"#ss3\">Special Session 3<\/a><\/td>\n<td class=\"poster\"><a href=\"#ps2\">Poster 2 + <i class=\"fas fa-mug-hot\"><\/i> coffee<\/a><\/td>\n<\/tr>\n<tr>\n<td>11:30 &#8211; 12:30<\/td>\n<td class=\"special\"><a href=\"#ss1\">Special Session 1<\/a><\/td>\n<td class=\"regular\"><a href=\"#rs3\">Regular Session 3<\/a><\/td>\n<td class=\"special\">\n<div>\n<div><a href=\"#ss5\">Special Session 5<\/a><\/div>\n<\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>12:30 &#8211; 12:50<\/td>\n<td>&nbsp;<\/td>\n<td>&nbsp;<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>12:50 &#8211; 14:00<\/td>\n<td class=\"lunch\"><i class=\"fas fa-utensils\"><\/i> Lunch Break<\/td>\n<td class=\"lunch\"><i class=\"fas fa-utensils\"><\/i> Lunch Break<\/td>\n<td class=\"lunch\"><i class=\"fas fa-utensils\"><\/i> Lunch Break<\/td>\n<\/tr>\n<tr>\n<td>14:00 &#8211; 15:00<\/td>\n<td class=\"regular\"><a href=\"#rs2\">Regular Session 2<\/a><\/td>\n<td class=\"regular\"><a href=\"#rs4\">Regular Session 4<\/a><\/td>\n<td class=\"regular\">\n<div>\n<div><a href=\"#rs6\">Regular Session 6<\/a><\/div>\n<\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>15:00 &#8211; 15:30<\/td>\n<td colspan=\"1\" rowspan=\"2\">\n<div><a href=\"#panel\">Panel<\/a><\/div>\n<\/td>\n<td class=\"special\" colspan=\"1\" rowspan=\"2\">\n<div><a href=\"#ss4\">Special Session 4<\/a><\/div>\n<\/td>\n<td class=\"coffee\"><i class=\"fas fa-mug-hot\"><\/i> Coffee Break<\/td>\n<\/tr>\n<tr>\n<td>15:30 &#8211; 16:00<\/td>\n<td class=\"regular\" colspan=\"1\" rowspan=\"3\">\n<div><a href=\"#rs7\">Regular Session 7<\/a><\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>16:00 &#8211; 16:30<\/td>\n<td class=\"poster\" colspan=\"1\" rowspan=\"3\">\n<div><a href=\"#ps1\">Poster 1 + <i class=\"fas fa-mug-hot\"><\/i> coffee<\/a><\/div>\n<\/td>\n<td class=\"coffee\"><i class=\"fas fa-mug-hot\"><\/i> Coffee Break<\/td>\n<\/tr>\n<tr>\n<td>16:30 &#8211; 16:50<\/td>\n<td class=\"social\" colspan=\"1\" rowspan=\"6\">\n<div><a href=\"https:\/\/orion.polito.it\/iolts\/social-activities\/\"><i class=\"fas fa-champagne-glasses\"><\/i> Social Event and Gala Dinner<\/a><\/div>\n<\/td>\n<\/tr>\n<tr>\n<td>16:50 &#8211; 17:00<\/td>\n<td class=\"closing\" colspan=\"1\" rowspan=\"1\">\n<div>Closing<\/div>\n<\/td>\n<\/tr>\n\n<tr>\n<td>17:00 &#8211; 18:00<\/td>\n<td class=\"special\" colspan=\"1\" rowspan=\"1\">\n<div><a href=\"#ss2\">Special Session 2<\/a><\/div>\n<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>18:00 &#8211; 19:30<\/td>\n<td>&nbsp;<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>19:30 &#8211; 21:30<\/td>\n<td class=\"welcome\" colspan=\"1\" rowspan=\"1\">\n<div><a href=\"https:\/\/orion.polito.it\/iolts\/social-activities\/\"><i class=\"fas fa-champagne-glasses\"><\/i>  Welcome reception<\/a><\/div>\n<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<tr>\n<td>21:00 &#8211; 24:00<\/td>\n<td>&nbsp;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"k1\">Keynote 1<\/h2>\n\n\n\n<p>Moderator: Angeliki Kritikakou (University of Rennes, France)<\/p>\n\n\n\n<p><a href=\"https:\/\/orion.polito.it\/iolts\/keynote\/#Aida-Todri-Sanial\"><strong>Unlocking the potential of emergent and collective dynamics for physical computing<\/strong><br>Aida Todri-Sanial (NanoComputing Research Lab, Integrated Circuits, EE Dept., TU\/e, NL) <\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"k2\">Keynote 2<\/h2>\n\n\n\n<p>Moderator: Leticia Bolzani P\u00f6hls (IHP, Germany)<\/p>\n\n\n\n<p><a href=\"https:\/\/orion.polito.it\/iolts\/keynote\/#Cecilia-Metra\"><strong>AI Reliability, Safety, and Security Challenges for a Trustworthy Metaverse<\/strong><br>Cecilia Metra (Universit\u00e0 di Bologna, IT)<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs1\">Regular Session 1: \u201cDesign for Security and Reliability\u201d<\/h2>\n\n\n\n<p>Moderator: Paolo Maistri (TIMA \/ CNRS, France)<\/p>\n\n\n\n<p><strong>Securing the Control of Digital Beamforming<\/strong><br>Love BARANY (Lund University), William ERIKSSON (BeammWave AB), Joel \u00c5HLUND (Advenica AB), Daniel BAKIC (BeammWave AB), Erik LARSSON (Lund University), Joakim AXMON, Markus T\u00f6RM\u00e4NEN (BeammWave AB)<\/p>\n\n\n\n<p><strong>TIMA-PUF: Time Measurement based Arbiter PUF<\/strong><br>Azzadine THAJTE (TIMA), Laurent FESQUET (TIMA laboratory), Giorgio DI NATALE (TIMA)<\/p>\n\n\n\n<p><strong>Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules<\/strong><br>Alessandro PALUMBO (CentraleSup\u00e9lec)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs2\">Regular Session 2: \u201cResistive memories and CIM reliability\u201d<\/h2>\n\n\n\n<p>Moderator: George Papadimitriou (University of Patras, Greece)<\/p>\n\n\n\n<p><strong>Improving Error Correction with Weak-Bit-Information in Resistive Memories<\/strong><br>Valentin GHERMAN (CEA LIST), Ishai NAVEH (Weebit Nano Ltd), Bastien GIRAUD (CEA), Antoine HEBERT (CEA LIST), Gabriel MOLAS, Giuseppe PICCOLBONI, Zeev FREIDIN, Amir REGEV, Matan GUTTMAN, Ilan SEVER (Weebit Nano Ltd)<\/p>\n\n\n\n<p><strong>Adaptive Testing of Compute-in-Memory Based CNNs Using Probabilistic Test Acceptance Limits<\/strong><br>Anurup SAHA (Georgia Tech), Kwondo MA (Rebellions), Chandramouli AMARNATH (Google), Moinuddin QURESHI, Abhijit CHATTERJEE (Georgia Institute of Technology)<\/p>\n\n\n\n<p><strong>ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators<\/strong><br>Jianan WEN (Leibniz Institute for High Performance Microelectronics), Andrea BARONI, Alberto MISTRONI (IHP &nbsp;Leibniz Institut f\u00fcr innovative Mikroelektronik), Eduardo PEREZ (IHP-Leibniz-Institut f\u00fcr innovative Mikroelektronik), Cristian ZAMBELLI (Universit\u00e0 degli Studi di Ferrara), Christian WENGER (IHP &nbsp;Leibniz Institut f\u00fcr innovative Mikroelektronik), Milos KRSTIC (IHP), Leticia Maria BOLZANI P\u00f6HLS (IHP &nbsp;Leibniz Institut f\u00fcr innovative Mikroelektronik)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs3\">Regular Session 3: \u201cMemory test, diagnosis, and security\u201d<\/h2>\n\n\n\n<p>Moderator: Lorena Anghel (Grenoble INP &#8211; SPINTEC, France)<\/p>\n\n\n\n<p><strong>A Runtime Efficient Graph-Based Cell-Aware Model Generation for Structural SRAM Testing<\/strong><br>Gianmarco MONGELLI, Xhesila XHAFA (LIRMM), Eric FAEHN, Dylan ROBINS (STM), Patrick GIRARD, Arnaud VIRAZEL (LIRMM)<\/p>\n\n\n\n<p><strong>Fault Diagnosis in ReCAM Arrays<\/strong><br>Haneen G. HEZAYYIN (Karlsruhe Institute of Technology), Mahta MAYAHINIA (KIT university), Mehdi TAHOORI (Karlsruhe Institute of Technology)<\/p>\n\n\n\n<p><strong>Body Bias Injection on the FLASH Memory Accelerator of a 32-bit Microcontroller<\/strong><br>ZILING LIAO, Philippe MAURINE (LIRMM), Florent BRUGUIER (Universite de Montpellier)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs4\">Regular Session 4: \u201cNN reliability and security\u201d<\/h2>\n\n\n\n<p>Moderator: Mohammadreza Heidari Iman (TIMA Laboratory, France)<\/p>\n\n\n\n<p><strong>Fault Tolerance in Quantized and Pruned Convolutional Neural Networks<\/strong><br>Wilfread GUILLEM\u00e9 (Univ. Rennes, INRIA, IRISA), Angeliki KRITIKAKOU (Univ Rennes, INRIA, Irisa), Youri HELEN (DGA MI), CEDRIC KILLIAN (Universit\u00e9 Jean Monnet Saint-Etienne), Daniel CHILLET (University of Rennes 1, IRISA\/INRIA)<\/p>\n\n\n\n<p><strong>NAPER: Fault Protection for Real-Time Resource-Constrained Deep Neural Networks<\/strong><br>Rian Adam RAJAGEDE, Muhammad Husni SANTRIAJI (University of Central Florida), Muhammad Arya FIKRIANSYAH, Hilal Hudan NUHA (Telkom University), Yanjie FU (Arizona State University), Yan SOLIHIN (University of Central Florida)<\/p>\n\n\n\n<p><strong>STDP-Trained Spiking Neural Network Reliability Assessment Through Fault Injections<\/strong><br>Zalfa JOUNI (Sorbonne Universit\u00e9, CNRS, LIP6, Paris, France), Haralampos STRATIGOPOULOS (Sorbonne Univ., CNRS, LIP6)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs5\">Regular Session 5: \u201cSoft errors\u201d<\/h2>\n\n\n\n<p>Moderator: Haralampos Stratigopoulos (Sorbonne Universit\u00e9 \/ CNRS \/ LIP6, France)<\/p>\n\n\n\n<p><strong>Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration<\/strong><br>Foteini KOTSIMPOU, George PAPADIMITRIOU, Dimitris GIZOPOULOS (University of Athens)<\/p>\n\n\n\n<p><strong>Bloom Filter-Based Soft Error Detection in Instruction memory: Insights from Neutron Beam and FI campaigns<\/strong><br>Elijah CISHUGI, Tijmen T. SMIT, Bruno ENDRES FORLIN (University of Twente), Cazzaniga CARLO (Rutherford Appleton Laboratory-ISIS), Kuan-Hsun CHEN (University of Twente), Marco OTTAVI (Twente U.)<\/p>\n\n\n\n<p><strong>Leveraging Open-Source Bitstream Documentation for FPGA Soft-Error Robustness Analysis<\/strong><br>Christian FIBICH, Leonardo LOVRIC (University of Applied Sciences Technikum Wien)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs6\">Regular Session 6: \u201cSecurity\u201d<\/h2>\n\n\n\n<p>Moderator: Maria Mushtaq (Telecom Paris, France)<\/p>\n\n\n\n<p><strong>PLL Over-Clocking Through Repeated Fault Injections<\/strong><br>Louis DUBOIS (LIRMM &#8211; ANSSI &#8211; DGA), Philippe MAURINE (LIRMM)<\/p>\n\n\n\n<p><strong>Side-Channel Extraction of Dataflow AI Accelerator Hardware Parameters<\/strong><br>Guillaume LOMET (Inria), Ruben SALVADOR (INRIA), Brice COLOMBIER (Universit\u00e9 Jean Monnet Saint-Etienne), Vincent GROSSO (Laboratoire Hubert Curien), Olivier SENTIEYS (INRIA), CEDRIC KILLIAN (Universit\u00e9 Jean Monnet Saint-Etienne)<\/p>\n\n\n\n<p><strong>AI-based Classification of Intentional vs. Unintentional Corruptions in the Split Computing context<\/strong><br>Giuseppe ESPOSITO, Enrico MAGLIANO, Nicola SCARANO, Tamer AHMED ELTARAS, Juan GUERRERO, Stefano DI CARLO (Politecnico di Torino), Marco LEVORATO (University of California Irvine), Luca MANNELLA, Josie RODRIGUEZ CONDIA, Alessandro SAVINO, Matteo SONZA REORDA (Politecnico di Torino)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"rs7\">Regular Session 7: \u201cOnline monitoring and Functional Safety\u201d<\/h2>\n\n\n\n<p>Moderator: Erik Larsson (Lund University, Sweden)<\/p>\n\n\n\n<p><strong>On-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems<\/strong><br>Martin Eugenio OMANA (University of Bologna), Alex MENGHI (Hera Group), Alessandro STEFANI (Zivan SRL), Enrico VICINI (Micron Technology), Cecilia METRA (University of Bologna), Giuseppe FROIO (Marvell Technology), Stefano PETRUCCI (Intel Corp.)<\/p>\n\n\n\n<p><strong>NAVIgator: Exploring the Voltage Limits of AMD NAVI GPUs for Energy Efficient Computing<\/strong><br>Maria TRAKOSA, Odysseas CHATZOPOULOS, George PAPADIMITRIOU, Dimitris GIZOPOULOS (University of Athens)<\/p>\n\n\n\n<p><strong>Real-Time Fault Analysis in RISC-V Processors: A Case Study Using the Internal State Monitor<\/strong><br>Roua BOULIFA, Giorgio DI NATALE (TIMA), Paolo MAISTRI (CNRS)<\/p>\n\n\n\n<p><strong>Lightweight Concurrent Out-of-Distribution Detection in Hyperdimensional Computing Hardware<\/strong><br>Mahboobe SADEGHIPOURRUDSARI, vincent MEYERS (Karlsruher Institut f\u00fcr Technologie (KIT)), Mehdi TAHOORI (Karlsruhe Institute of Technology)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ps1\">Poster Session 1<\/h2>\n\n\n\n<p><strong>A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation<\/strong><br>Dorian RONGA, Xhesila XHAFA (LIRMM), Eric FAEHN (STM), Patrick GIRARD (LIRMM), Thibault VAYSSADE (Univ. Montpellier, CNRS, LIRMM), Arnaud VIRAZEL (LIRMM)<\/p>\n\n\n\n<p><strong>Anomalous IoT Behavior Detection Based on SARIMA Reference Waveform<\/strong><br>Ryusei EDA, Nozomu TOGAWA (Waseda University)<\/p>\n\n\n\n<p><strong>CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus<\/strong><br>Oberti FRANCO (Dumarey), Stefano DI CARLO, Alessandro SAVINO (Politecnico di Torino)<\/p>\n\n\n\n<p><strong>Comparative Analysis of TID Effects in a&nbsp; nm FD-SOI Process under Gamma-Ray and Alpha-Ray Irradiation<\/strong><br>Hikaru NAKAMOTO, Taiki OZAWA, Ryuichi NAKAJIMA, Haruto SUGISAKI, Keita YOSHIDA (Kyoto Institute of Technology), Jun FURUTA (Okayama Prefectural University), Kazutoshi KOBAYASHI (Kyoto Institute of Technology)<\/p>\n\n\n\n<p><strong>Dose Effects and Mitigation in nm FD-SOI Advanced Interface Bus Chiplet Interconnect<\/strong><br>Antoine ROUGET, Fady ABOUZEID (STMicroelectronics), Adrian EVANS (CEA), Victor MALHERBE (STMicroelectronics), Aleksandra CHUMAKOVA (ESRF), Philippe ROCHE (STMicroelectronics), Fabien CLERMIDY (CEA-LETI)<\/p>\n\n\n\n<p><strong>GPD: Predictive control flow error detection leveraging data flow error detection methods<\/strong><br>Raghunandana K, Yogesh Prasad R (Indian Space Research Organisation), Matteo SONZA REORDA (Politecnico di Torino), Virendra SINGH (Indian Institute of Technology Bombay)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ps2\">Poster Session 2<\/h2>\n\n\n\n<p><strong>Leveraging Image-based Transformations to Mitigate Adversarial Attacks in AI-based Safety-critical Systems<\/strong><br>Mart\u00ed CARO (Barcelona Supercomputing Center (BSC-CNS)), Axel BRANDO (Barcelona Supercomputing Center (BSC)), JAUME ABELLA (Barcelona Supercomputing Center (BSC-CNS))<\/p>\n\n\n\n<p><strong>Machine Learning-Based Parametric Fault Detectionin Analog and Mixed-Signal Circuits<\/strong><br>JULES KOUAMO, Emmanuel SIMEU (TIMA Laboratory), Michele PORTOLAN (Siemens)<\/p>\n\n\n\n<p><strong>On the validity of SEE simulation for rad-hard analog ASICs<\/strong><br>Valentin GUTIERREZ, Gildas LEGER (IMSE-CNM), Antonio GINES (IMSE-CNM (CSIC, Universidad de Sevilla)), Carlos DOMINGUEZ (IMSE-CNM), Eduardo PERALIAS (Instituto de Microelectronica de Sevilla (IMSE-CNM))<\/p>\n\n\n\n<p><strong>PUFzzify: A Fuzzy Logic-Based System for Detecting Trustable Physical Unclonable Functions<\/strong><br>Mohammad Reza HEIDARI IMAN (TIMA Lab), Sergio VINAGRERO (INL), Elena Ioana VATAJELU (TIMA Laboratory), Giorgio DI NATALE (TIMA)<\/p>\n\n\n\n<p><strong>SHIELD: PSO-Based Hardware Trojan DetectIon for Efficient and Low-Cost Defense<\/strong><br>Mostafa HOSSEINI (University of Zanjan), Ali AZARPEYVAND, Mahdi TAHERI (Tallinn University of Technology), Tara GHASEMPOURI (Talinn University of Technology), Maksim JENIHHIN (Tallinn University of Technology)<\/p>\n\n\n\n<p><strong>Side-Channel Attack Detection using gem5 and Machine Learning: A Case Study on Fault-based Attacks in RISC-V<\/strong><br>Mahreen KHAN (Institut Polytechnique de Paris), Maria MUSHTAQ (Telecom Paris), Renaud PACALET, Ludovic APVRILLE (Telecom Paris, Institut Polytechnique de Paris)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ss1\"><strong>Special Session 1: \u201c<\/strong>Robust Quantum Neural Networks: Innovations in Design, Optimization, and Applications\u201d<\/h2>\n\n\n\n<p>Moderator: Alberto Marchisio, New York University Abu Dhabi<\/p>\n\n\n\n<p><strong>Benchmarking for Robustness: A Compass for Quantum Neural Network Development<\/strong><br>Jean Senellart, Quandela<\/p>\n\n\n\n<p><strong>Quantum AI: Harnessing the Power of Quantum Computing for Scalable and Adaptive Learning<\/strong><br>Samuel Yen-Chi Chen, Wells Fargo<\/p>\n\n\n\n<p><strong>Towards Next-Generation Quantum Neural Networks: Enhancing Efficiency, Security, and Privacy<\/strong><br>Mohamed Bennai, Hassan II University of Casablanca<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ss2\">Special Session 2: \u201cResilient and Energy-Efficient Computing with Neuromorphic Systems\u201d<\/h2>\n\n\n\n<p>Moderator: Aida Todri-Sanial (NanoComputing Research Lab, Integrated Circuits, EE Dept., TU\/e, NL)<\/p>\n\n\n\n<p><strong>Building Resilient AI: Strengthening Data, Security, and Robustness in Neural Networks<\/strong><br>Kaushik Roy, Purdue University<\/p>\n\n\n\n<p><strong>Dynamic Neuromorphic Processing for Energy-Efficient Cognitive Sensing<\/strong><br>Amir Zjajo, Innantera<\/p>\n\n\n\n<p><strong>Neuromorphic Computing for Embodied Intelligence in Autonomous Systems: Current Trends, Challenges, and Future Directions<\/strong><br>Muhammad Shafique, New York University (NYU) Abu Dhabi<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ss3\">Special Session 3: \u201cSilent Data Corruptions in Data Parallel Architectures at Scale\u201d<\/h2>\n\n\n\n<p>Moderator: Dimitris Gizopoulos (University of Athens)<\/p>\n\n\n\n<p><strong>Recent advances in SDC detection at Hyperscale<\/strong><br>Harish D. Dixit and Sriram Sankar (Meta Platforms)<\/p>\n\n\n\n<p><strong>Accurate Analysis of Silent Data Corruptions in Programmable AI Accelerator Microarchitectures<\/strong><br>Odysseas Chatzopoulos, Maria Trakosa, and Dimitris Gizopoulos (University of Athens)<\/p>\n\n\n\n<p><strong>When Silicon Fails Silently: Characterizing Hardware-Induced Corruption in LLM Training<\/strong>\u201d<br>Leonard Lausen, Jeffrey Jian Ma, Hengzhi Pei, George Karypis (Amazon)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ss4\">Special Session 4: \u201cSCAR &#8211; Hardware and Physical Automotive Security\u201d<\/h2>\n\n\n\n<p>Moderator: Stefano Di Carlo (Politecnico di Torino, Italy)<\/p>\n\n\n\n<p><strong>On Post-Quantum Attribute-based Encryption for Automotive Over-the-Air Software Updates<\/strong><br>Gianluca Dini (University of Pisa), Salvatore Lombardi (University of Pisa), Tommaso Antonini (University of Pisa)<\/p>\n\n\n\n<p><strong>Autoencoder-Based Detection of Physical-Layer Anomalies in Automotive CAN Networks<\/strong><br>Antonio Battaglia (University of Messina, Italy), Nicasio Canino (University of Pisa, Italy), Pierpaolo Dini (University of Pisa, Italy), Giovanni Lombardo (University of Messina, Italy), Francesco Longo (University of Messina, Italy), and Daniele Rossi (University of Pisa, Italy)<\/p>\n\n\n\n<p><strong>Exploiting Reconfigurable Intelligent Surfaces to Achieve Multi-Receiver Physical Layer Security<\/strong><br>Simone Marrocco (University of Trento, Italy), Paolo Casari (University of Trento, Italy), Michele Segata (University of Trento, Italy)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"ss5\">Special Session 5: \u201cSCAR &#8211; Security and privacy in the Automotive domain\u201d<\/h2>\n\n\n\n<p>Moderator: Ilaria Matteucci (CNR, Italy)<\/p>\n\n\n\n<p><strong>Towards Semantic Coherence: Understanding Cybersecurity and Digital Sovereignty in the Automotive Landscape<\/strong><br>Elisa Sorrentino, Anna Federica Spagnuolo, Alessio Portaro, Maria Taverniti, Elena Cardillo (Institute of Informatics and Telematics National Research Council)<\/p>\n\n\n\n<p><strong>Secure and Flexible WebAssembly Deployment Infrastructure for Automotive Cyber-Physical Systems<\/strong><br>Tancredi Orlando (University of Messina), Michele Arena (University of Messina), Luca D&#8217;Agati (University of Messina), Giovanni Merlino (University of Messina), Francesco Longo (University of Messina)<\/p>\n\n\n\n<p><strong>Human-Artificial Intelligence for Threat Modelling in the Automotive Domain<\/strong><br>Giampaolo Bella (Universityu of Catania, Italy), Gianpietro CASTIGLIONE (Universityu of Catania, Italy), Sergio ESPOSITO (Universityu of Catania, Italy), Mirko MANGANO (Universityu of Catania, Italy), Giacomo PAMPALLONA (Universityu of Catania, Italy), Mario RACITI (IMT School for Advanced Studies, Italy), Salvatore RICCOBENE (Universityu of Catania, Italy), Daniele SANTAMARIA (Universityu of Catania, Italy)<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"panel\">Panel: 3D-IC &amp; Chiplet Ecosystem: How to Guarantee Silicon Lifecycle Quality, Yield, Reliability and Security of CMOS- and Emerging Technology-Based Packages?<\/h2>\n\n\n\n<p><strong>Moderator:<\/strong> Cecilia Metra (Universit\u00e0 di Bologna, IT)<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Panelists:<\/h4>\n\n\n\n<p>Yervant Zorian (Synopsys), Leticia Bolzani P\u00f6hls (IHP, Germany), Giorgio DI NATALE (TIMA)<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Abstract:<\/h4>\n\n\n\n<p>Three-dimensional IC integration and chiplet-based packaging are key enablers for high-performance computing, AI accelerators, and ultra-low-power edge applications. By stacking heterogeneous chiplets via hyper-bonding, Through-Silicon Vias (TSVs), micro-bumps, &nbsp;or ultra-high-speed interfaces, such as UCIe 3 &amp; HBM 4, designers unlock unprecedented bandwidth, energy efficiency, and miniaturization. Meanwhile, novel device technologies, such as Resistive Random Access Memories (RRAMs), and emerging computing paradigms, including brain-inspired computing, such as Computation-in-Memory (CiM) and neuromorphic architectures, promise to address the limitations related to transistor miniaturization and the von Neumann bottleneck. Despite all these advantages, heterogeneous integration introduces challenges related to silicon lifecycle quality, yield, reliability ,and security.<\/p>\n\n\n\n<p>This panel brings together experts in heterogeneous integration of CMOS- and emerging technology-based systems to explore how the community can:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>&nbsp;Innovate test &amp; repair strategies at chiplet, interconnect and package levels to address, not only traditional, but also unique fault types related to manufacturing deviations aiming to maximize quality &amp; yield and minimize test cost Tackle new in-field fault types caused by time-dependent deviations, including environmental and temporal variations, when assuming the heterogeneity at chiplet, interconnect and package levels. <\/li>\n\n\n\n<li>Ensure reliability during lifetime by adopting novel Silicon Lifecycle Management strategies able to provide fault mitigation and tolerance at chiplet &amp; high-speed interconnect levels.<\/li>\n\n\n\n<li>Reinforce trust and security in chiplet-based 3D integration, where supply-chain threats and hardware Trojans become more acute. Chiplets are often sourced as known-good dies (KGDs) that undergo pre-shipment configuration\u2014analog tuning, PLL trimming, PUF enrollment, or secret key provisioning\u2014which creates assets that must be protected. These assets remain exposed during essential post-assembly test phases needed to detect new defects from stacking. This calls for secure online test approaches that complement conventional tests without compromising sensitive configurations.<\/li>\n\n\n\n<li>Ensure the trustworthiness of chiplets themselves, since traditional inspection and assurance methods\u2014like optical analysis\u2014are impractical at chiplet scale. New mechanisms are needed to authenticate and certify chiplets and interconnects, addressing the risk that a compromised die could undermine the entire stack.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>All sessions are scheduled according to the local time. Timeslot July 7 July 8 July 9 8:00 &#8211; 8:30 Registration&hellip;<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1950","page","type-page","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v23.4 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Technical Program - The 31st IEEE International Symposium on On-Line Testing and Robust System Design<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/orion.polito.it\/iolts\/technical-program\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Technical Program - The 31st IEEE International Symposium on On-Line Testing and Robust System Design\" \/>\n<meta property=\"og:description\" content=\"All sessions are scheduled according to the local time. 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