IOLTW 2000, Preliminary Program

6th IEEE International On-Line Testing Workshop
	IEEE Computer Society Test Technology Technical Council.	July 3-5, 2000, Mallorca,Spain.

General Chairs
M. Nicolaidis, TIMA Laboratory
J. Segura, U. Illes Balears Program Chairs
J.P. Hayes, U. of Michigan
D. Nikolos, U. Patras
Vice-General Chair
Y. Zorian, LogicVision Vice-Program Chairs
C. Metra, U. Bologna
Local Arrangements
E. García, U. Illes Balears Publicity
C. Lopez Barrio, Telefónica
Financial Chair
M. Roca, U. Illes Balears Publications
H. Vergos, U. Patras
Secretariat
E. Isern, U. Illes Balears ETTTC Liaison
C. Landrault, LIRMM

Program Committee

J. Abraham, U. Texas at Austin
M. Abramovici, Lucent Bell Labs
S.P. Athan, U. South Florida
E. Boehl, Robert Bosch GmbH
T.J. Chakraborty, Lucent Bell Labs
C. Dufaza, LIRMM
J. Figueras, U. P. de Catalunya
W.K. Fuchs, Purdue U.
D. Gizopoulos, U. Piraeus
M. Gössel, U. of Postdam
Th. Haniotakis, ISD
S. Hellebrand, U. Stuttgart
A. Ivanov, U. of Brit. Columbia
R. Iyer, U. Illinois
B. Kaminska, Fluence
R. Karri, New York U.
K. Kuchukian, Armenian NAS
D. Kagaris, Southern Illinois U.
P.K. Lala, U. of Arkansas
H. Levendel, Motorola
R. Leveugle, TIMA Laboratory
J.C. Lo, Rhode Island U. E. J. McCluskey, Stanford U.
Y. Maidon, U. Bordeaux
V.S.S. Nair, South. Methodist U.
T. Nanya, Tokyo Inst. of Techn.
A. Orailoglu, U. Cal. San Diego
A. Paschalis, U. Athens
S. Piestrak, T. U. of Wroclaw
P. Prinetto, Politec. di Torino
M. Rebaudengo, Politec. di Torino
K. Roy, Purdue U.
A.D. Singh, Auburn U.
E.S. Sogomonyan, Rus. A. of Sc.
M. Sonza Reorda, Politec. di Torino
G. Stamoulis, Intel
C.E. Stroud, U. Kentucky
E. Simeu, TIMA Laboratory
V. Szekely, T. U. of Budapest
S. Tragoudas, U. Southern Illinois
F. Vargas, PUCRS
R. Velazco, TIMA Laboratory
H.J. Wunderlich, U. Stuttgart

Monday July 3, 2000

07.30 - 08.30 Registration

08.30 - 08.40 Opening Address

08.40 - 09.10 Keynote Presentation:
Dependability Issues in the WWW,
Jacob Abraham, U. Texas at Austin

09.10 - 09.20
Break

09.20 - 10.20 Session 1: Fault Tolerance
Moderator: T.M. Mak, Intel

1.1. Micro-Checkpointing: A Checkpointing for Multithreaded Applications,
K. Whisnant, Z. Kalbarczyk, R.K. Iyer, Center for Reliable and High - Performance Computing, U. of Illinois at Urbana - Champaign

1.2. A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT,
A. Benso, S. Chiusano, P. Prinetto, Politecnico di Torino

1.3. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC and CISC based architectures,
M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco, Politecnico di Torino and TIMA Laboratory

10.20 - 10.40
Break

10.40 - 11.40 Session 2: Fault Tolerance and On-Line testing for Reconfigurable Systems
Moderator: Georges Stamoulis, Intel

2.1. Relation between Fault Tolerance and Reconfiguration in Cellular Systems,
V. Drabek, Brno U. of Technology

2.2. Improving On-Line BIST-Based Diagnosis for Roving STARs,
M. Abramovici, C. Stroud, B. Skaggs, J. Emmert, Bell Labs - Lucent Technologies and U. of Kentucky

2.3. Self-Testing of FPGA Delay Faults in the System Environment,
A. Krasniewski, Warsaw U. of Technology

11.40 - 12.00
Break

12.00 - 12.40 Session 3: Reliability Issues in Nanometer Technologies and Radiation Effects
Moderator: Cecilia Metra, U. Bologna

3.1. A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits,
J.A. Sainz, M. Roca, R. Muñoz, J.A. Maiz, L.A. Aguado, U. of the Basque Country and U. of Balearic Islands

3.2. An Overview of the Applications of a Pulsed Laser System for SEU Testing,
V. Pouget, P. Fouillat, D. Lewis, H. Lapuyade, L. Sarger, F.M. Roche, S. Duzellier, R. Ecoffet, U. of Bordeaux, U. of Montpellier, ONERA - DESP and CNES

12.40 - 14.00
Lunch

14.00 - 15.20 Session 4: Fault Injection
Moderator: Regis Leveugle, TIMA Laboratory

4.1. New Techniques for Accelerating Fault Injection in VHDL descriptions,
B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante, Politecnico di Torino

4.2. Estimating Circuit Fault - Tolerance by Means of Transient - Fault Injection in VHDL,
F. Vargas, A. Amory, R. Velazco, Catholic U. - PUCRS and TIMA Laboratory

4.3. A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System,
D. Gil, J. Gracia, J.C. Baraza, P.J. Gil, Polytechnic University of Valencia
4.4. Transient Bitflip Injection in Microprocessor Embedded Applications,
R. Velazco, S. Rezgui, TIMA Laboratory

15.20 - 15.40
Break

15.40 - 17.00 Session 5: On-Line Current Monitoring
Moderator: Andre Ivanov, U. of Brit. Columbia

5.1. On-line current testing for a microprocessor based application with an off-chip sensor,
B. Alorda, I. de Paul, J. Segura, T. Miller, U. of Balears Islands and Intel Corp.

5.2. I-V Fast Iddq Current Sensor for On-Line Mixed-Signal/Analog Test,
M. Margala, S. Dragic, A. Elabasiry, S. Ekpe, V. Stopjaková, U. of Alberta and Slovak U. of Technology

5.3. A Compact Built-In Current Sensor for Iddq Testing,
Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, ISD S.A. and U. of Patras

5.4. An Improved CMOS BICS for On-Line testing,
Y. Maidon, Y. Deval, J.B. Begueret, U. Bordeaux

19.30
Welcome Reception - Bellver Castle -

Tuesday July 4, 2000

08.30 - 09.30 Session 6: Concurrent Checking
Moderator: Bernd Straube, Fraunhofer IIS/EAS Dresden

6.1. Concurrent Scan Monitoring and Multi-Pattern Search,
J.M.V. dos Santos, ISEP - I. S. Engenharia do Porto

6.2. Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems,
A. Abdelhay, E. Simeu, TIMA Laboratory

6.3. Decomposition Approach to Designing FPGA-based Self-checking Control Units,
M. Karpovsky, I. Levin, V. Sinelnikov, Boston U., Tel-Aviv U. and Academic Technological Institute

09.30 - 09.50
Break

09.50 - 10.50 Session 7: Built-In Self Testing
Moderator: Christian Dufaza, LIRMM

7.1. Comparison between Random and Pseudo-Random Generation for BIST of Delay and Bridging Faults,
R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, U. of Montpellier

7.2. On Using Deterministic Test Sets in BIST,
O. Novak, J. Nosek, Technical U. of Liberec

7.3. Power Reduction in Test-Per-Scan BIST,
X. Zhang, K. Roy, Synopsys Inc. and Purdue U.

10.50 - 11.10
Break

11.10 - 12.40 Panel: Defect Driven Testing: IDDX and what else ?
Co-organized with IEEE D&T of Computers
Organizer: Joan Figueras, UPC
Moderator: Yervant Zorian, LogicVision

Panelists: Eberhard Boehl, Robert Bosch GmbH
Hans Manhaeve, QStar
Michael Nicolaidis, TIMA Laboratory
Jaume Segura, U. Illes Balears
Chuck Hawkins, U. New Mexico

12.40 - 14.00
Lunch

14.00 - 15.20 Session 8: Self Checking Circuits and Analog
Moderator: Parag K. Lala, U. of Arkansas

8.1. New Self-checking Circuits by Use of Berger Codes,
A. Morozov, V. Saposhnikov, Vl. Saposhnikov, M. Gössel, U. of Potsdam and Railway Transportation State U.

8.2. A new method for concurrent checking by use of a 1-out-of-4 code,
M. Gössel, Vl. Saposhnikov, A. Dmitriev, V. Saposhnikov, U. of Potsdam and Railway Transportation State U.

8.3. Self-checking FSM design with observing only FSM outputs,
A. Matrosova, S. Ostanin, Tomsk State U.
8.4. Faster time to market, lower cost of development and test for standard analog IC,
P. Migliavacca, STMicroelectronics

16.00
Social Event - Tour and Dinner -

Wednesday July 5, 2000

09.00 - 10.00 Session 9: Coding Theory and Applications
Moderator: Stanislaw Piestrak, T. U. of Wroclaw

9.1. Theoretical performance bounds of a probability of error estimator in digital links employing binary block codes,
K.D.R. Jagath-Kumara, Massey U., New Zealand

9.2. A Stamping Technique to Increase the Error Correcting Capacity of the (127,k,d) RS code,
T. Vallino, A. Dandache, J-P. Delahaye, F. Monteiro, B. Lepley, LICM / CLOES / SUPELEC and TDF - C2R

9.3. Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes,
D. Das, N.A. Touba, M. Seuring, M. Gössel, U. of Texas at Austin and U. of Potsdam

10.00 - 10.20
Break

10.20 - 11.20 Session 10: Fault Tolerance and On-Line Testing in Railway and Industrial Control
Moderator: TBD,

10.1. A Very Flexible DSP-Based Controller to On-Line Test and Control Industrial Process,
E. Nillesen, A. Del Pizzo, M. Pasquariello, R. Rizzo, Eindhoven U. of Technology and "Federico II" U. of Napoli

10.2. On Realization of Fault-Tolerant Fuzzy Controllers,
N. Kamiura, M. Tomita, N. Matsui, Himeji Institute of Technology

10.3. ISIS: A Fail - Safe Interface Realised in Smart Power Technology,
M. Nicolaidis, N. Zaidan, T. Calin, D. Bied - Charreton, TIMA Laboratory and INRETS

11.20 - 11.40
Break

11.40 - 12.40 Session 11: On-Line Testing and Self Repair
Moderator: TBD,

11.1. High level synthesis methodology for on-line testability optimization,
M.A. Naal, E. Simeu, TIMA Laboratory

11.2. Improving Fault Coverage in System Test,
J. Sosnowski, Warsaw U. of Technology

11.3. A Family of Self-Repair SRAM Cores,
A. Benso, S. Chiusano, G. di Natale, P. Prinetto, Politecnico di Torino

12.40 - 14.00
Lunch

General Chairs M. Nicolaidis, TIMA Laboratory J. Segura, U. Illes Balears	Program Chairs J.P. Hayes, U. of Michigan D. Nikolos, U. Patras
Vice-General Chair Y. Zorian, LogicVision	Vice-Program Chairs C. Metra, U. Bologna
Local Arrangements E. García, U. Illes Balears	Publicity C. Lopez Barrio, Telefónica
Financial Chair M. Roca, U. Illes Balears	Publications H. Vergos, U. Patras
Secretariat E. Isern, U. Illes Balears	ETTTC Liaison C. Landrault, LIRMM

Monday July 3, 2000
07.30 - 08.30	Registration
08.30 - 08.40	Opening Address
08.40 - 09.10	Keynote Presentation: Dependability Issues in the WWW, Jacob Abraham, U. Texas at Austin
09.10 - 09.20	Break
09.20 - 10.20	Session 1: Fault Tolerance Moderator: T.M. Mak, Intel
1.1.	Micro-Checkpointing: A Checkpointing for Multithreaded Applications, K. Whisnant, Z. Kalbarczyk, R.K. Iyer, Center for Reliable and High - Performance Computing, U. of Illinois at Urbana - Champaign
1.2.	A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT, A. Benso, S. Chiusano, P. Prinetto, Politecnico di Torino
1.3.	Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC and CISC based architectures, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco, Politecnico di Torino and TIMA Laboratory
10.20 - 10.40	Break
10.40 - 11.40	Session 2: Fault Tolerance and On-Line testing for Reconfigurable Systems Moderator: Georges Stamoulis, Intel
2.1.	Relation between Fault Tolerance and Reconfiguration in Cellular Systems, V. Drabek, Brno U. of Technology
2.2.	Improving On-Line BIST-Based Diagnosis for Roving STARs, M. Abramovici, C. Stroud, B. Skaggs, J. Emmert, Bell Labs - Lucent Technologies and U. of Kentucky
2.3.	Self-Testing of FPGA Delay Faults in the System Environment, A. Krasniewski, Warsaw U. of Technology
11.40 - 12.00	Break
12.00 - 12.40	Session 3: Reliability Issues in Nanometer Technologies and Radiation Effects Moderator: Cecilia Metra, U. Bologna
3.1.	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits, J.A. Sainz, M. Roca, R. Muñoz, J.A. Maiz, L.A. Aguado, U. of the Basque Country and U. of Balearic Islands
3.2.	An Overview of the Applications of a Pulsed Laser System for SEU Testing, V. Pouget, P. Fouillat, D. Lewis, H. Lapuyade, L. Sarger, F.M. Roche, S. Duzellier, R. Ecoffet, U. of Bordeaux, U. of Montpellier, ONERA - DESP and CNES
12.40 - 14.00	Lunch
14.00 - 15.20	Session 4: Fault Injection Moderator: Regis Leveugle, TIMA Laboratory
4.1.	New Techniques for Accelerating Fault Injection in VHDL descriptions, B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante, Politecnico di Torino
4.2.	Estimating Circuit Fault - Tolerance by Means of Transient - Fault Injection in VHDL, F. Vargas, A. Amory, R. Velazco, Catholic U. - PUCRS and TIMA Laboratory
4.3.	A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System, D. Gil, J. Gracia, J.C. Baraza, P.J. Gil, Polytechnic University of Valencia
4.4.	Transient Bitflip Injection in Microprocessor Embedded Applications, R. Velazco, S. Rezgui, TIMA Laboratory
15.20 - 15.40	Break
15.40 - 17.00	Session 5: On-Line Current Monitoring Moderator: Andre Ivanov, U. of Brit. Columbia
5.1.	On-line current testing for a microprocessor based application with an off-chip sensor, B. Alorda, I. de Paul, J. Segura, T. Miller, U. of Balears Islands and Intel Corp.
5.2.	I-V Fast Iddq Current Sensor for On-Line Mixed-Signal/Analog Test, M. Margala, S. Dragic, A. Elabasiry, S. Ekpe, V. Stopjaková, U. of Alberta and Slovak U. of Technology
5.3.	A Compact Built-In Current Sensor for Iddq Testing, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, ISD S.A. and U. of Patras
5.4.	An Improved CMOS BICS for On-Line testing, Y. Maidon, Y. Deval, J.B. Begueret, U. Bordeaux
19.30	Welcome Reception - Bellver Castle -

Tuesday July 4, 2000
08.30 - 09.30	Session 6: Concurrent Checking Moderator: Bernd Straube, Fraunhofer IIS/EAS Dresden
6.1.	Concurrent Scan Monitoring and Multi-Pattern Search, J.M.V. dos Santos, ISEP - I. S. Engenharia do Porto
6.2.	Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems, A. Abdelhay, E. Simeu, TIMA Laboratory
6.3.	Decomposition Approach to Designing FPGA-based Self-checking Control Units, M. Karpovsky, I. Levin, V. Sinelnikov, Boston U., Tel-Aviv U. and Academic Technological Institute
09.30 - 09.50	Break
09.50 - 10.50	Session 7: Built-In Self Testing Moderator: Christian Dufaza, LIRMM
7.1.	Comparison between Random and Pseudo-Random Generation for BIST of Delay and Bridging Faults, R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, U. of Montpellier
7.2.	On Using Deterministic Test Sets in BIST, O. Novak, J. Nosek, Technical U. of Liberec
7.3.	Power Reduction in Test-Per-Scan BIST, X. Zhang, K. Roy, Synopsys Inc. and Purdue U.
10.50 - 11.10	Break
11.10 - 12.40	Panel: Defect Driven Testing: IDDX and what else ? Co-organized with IEEE D&T of Computers Organizer: Joan Figueras, UPC Moderator: Yervant Zorian, LogicVision
Panelists:	Eberhard Boehl, Robert Bosch GmbH Hans Manhaeve, QStar Michael Nicolaidis, TIMA Laboratory Jaume Segura, U. Illes Balears Chuck Hawkins, U. New Mexico
12.40 - 14.00	Lunch
14.00 - 15.20	Session 8: Self Checking Circuits and Analog Moderator: Parag K. Lala, U. of Arkansas
8.1.	New Self-checking Circuits by Use of Berger Codes, A. Morozov, V. Saposhnikov, Vl. Saposhnikov, M. Gössel, U. of Potsdam and Railway Transportation State U.
8.2.	A new method for concurrent checking by use of a 1-out-of-4 code, M. Gössel, Vl. Saposhnikov, A. Dmitriev, V. Saposhnikov, U. of Potsdam and Railway Transportation State U.
8.3.	Self-checking FSM design with observing only FSM outputs, A. Matrosova, S. Ostanin, Tomsk State U.
8.4.	Faster time to market, lower cost of development and test for standard analog IC, P. Migliavacca, STMicroelectronics
16.00	Social Event - Tour and Dinner -

Wednesday July 5, 2000
09.00 - 10.00	Session 9: Coding Theory and Applications Moderator: Stanislaw Piestrak, T. U. of Wroclaw
9.1.	Theoretical performance bounds of a probability of error estimator in digital links employing binary block codes, K.D.R. Jagath-Kumara, Massey U., New Zealand
9.2.	A Stamping Technique to Increase the Error Correcting Capacity of the (127,k,d) RS code, T. Vallino, A. Dandache, J-P. Delahaye, F. Monteiro, B. Lepley, LICM / CLOES / SUPELEC and TDF - C2R
9.3.	Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes, D. Das, N.A. Touba, M. Seuring, M. Gössel, U. of Texas at Austin and U. of Potsdam
10.00 - 10.20	Break
10.20 - 11.20	Session 10: Fault Tolerance and On-Line Testing in Railway and Industrial Control Moderator: TBD,
10.1.	A Very Flexible DSP-Based Controller to On-Line Test and Control Industrial Process, E. Nillesen, A. Del Pizzo, M. Pasquariello, R. Rizzo, Eindhoven U. of Technology and "Federico II" U. of Napoli
10.2.	On Realization of Fault-Tolerant Fuzzy Controllers, N. Kamiura, M. Tomita, N. Matsui, Himeji Institute of Technology
10.3.	ISIS: A Fail - Safe Interface Realised in Smart Power Technology, M. Nicolaidis, N. Zaidan, T. Calin, D. Bied - Charreton, TIMA Laboratory and INRETS
11.20 - 11.40	Break
11.40 - 12.40	Session 11: On-Line Testing and Self Repair Moderator: TBD,
11.1.	High level synthesis methodology for on-line testability optimization, M.A. Naal, E. Simeu, TIMA Laboratory
11.2.	Improving Fault Coverage in System Test, J. Sosnowski, Warsaw U. of Technology
11.3.	A Family of Self-Repair SRAM Cores, A. Benso, S. Chiusano, G. di Natale, P. Prinetto, Politecnico di Torino
12.40 - 14.00	Lunch