| 7th IEEE International On-Line Testing Workshop |  |
| Ramada Hotel - Giardini Naxos - Taormina (Italy),
July 9-11, 2001 |
|
General Chair M. Nicolaidis, TIMA Laboratory C.Metra, U. Bologna |
Program Chairs J.P. Hayes, U. of Michigan D. Nikolos, U. Patras |
|
Vice General Chair Y. Zorian, LogicVision |
Vice Program Chair M.Sonza Reorda, Politec. di Torino |
|
Local Chair S. Pennisi, U. Catania |
Publicity D. Gizopoulos, U. Piraeus |
|
Financial Chair A. Imbruglia, STMicroelectronics |
Publications H. Vergos, U. Patras |
|
Secretariat R. Mambelli, U. Bologna |
ETTTC Liaison C. Landrault, LIRMM |
Program Committee
|
J. Abraham, U. Texas at Austin M. Abramovici, Lucent Bell Labs S.P. Athan, U. South Florida E. Boehl, Robert Bosch GmbH T.J. Chakraborty, Lucent Bell Labs J. Figueras, U.P. de Catalunya P. Girard, LIRMM D. Gizopoulos, U. Piraeus M. Gössel, U. of Postdam Th. Haniotakis, ISD S. Hellebrand, U. Stuttgart A. Ivanov, U. of Brit. Columbia R. Iyer, U. Illinois D. Kagaris, Southern Illinois U. R. Karri, New York U. A. Krasniewski, Warsaw U. of Tec. K. Kuchukian, Armenian NAS P.K. Lala, U. of Arkansas H. Levendel, Motorola R. Leveugle, TIMA Laboratory I. Levin, Tel Aviv U. J.C. Lo, Rhode Island U. |
E. J. McCluskey, Stanford U. Y. Maidon, U. Bordeaux H. Manhaeve, QStar A. Orailoglu, U. Cal. San Diego A. Paschalis, U. Athens S. Piestrak, T.U. of Wroclaw M. Rebaudengo, Politec. di Torino K. Roy, Purdue U. J. Segura, U. Illes Balears E. Simeu, TIMA Laboratory E.S. Sogomonyan, Rus. A. of Sc. J. Sosnowski, Warsaw U. of Tec. G. Stamoulis, Intel B. Straube, Fraunhofer IIS/EAS C.E. Stroud, U.N. Carolina at Charlotte N.A. Touba, U. Texas S. Tragoudas, U. Southern Illinois Y. Tsiatouhas, ISD F. Vargas, PUCRS R. Velazco, TIMA Laboratory H.T. Vierhaus, Brandenburg T.U. H.J. Wunderlich, U. Stuttgart |
Monday July 9, 2001. | |
| 07.30 - 08.30 | Registration |
| 08.30 - 08.40 | Opening Address |
| 08.40 - 09.40 | Keynote Presentations: Barry W. Johnson, U. of Virginia
S. Russo, STMicroelectronics |
| 09.40 - 10.00 | Coffee Break |
| 10.00 - 11.20 | Session 1: Dependability Evaluation Moderator: Jacob Abraham, U. Texas at Austin Coordinator: Diego Marino, Alstom Transport |
| 1.1. | Validation of a Software Dependability Tool via Fault Injection Experiments A. Benso, S. Di Carlo, G. Di Natale, L. Tagliaferri, P. Prinetto Politecnico di Torino |
| 1.2. | Exploiting FPGA for Accelerating Fault Injection Experiments P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante Politecnico di Torino |
| 1.3. | Path-Based Error Coverage Prediction J. Aidemark, P. Folkesson, J. Karlsson Chalmers University of Technology |
| 1.4. | Analyzing Fault Effects in Fault Insertion Experiments P. Gawkowski, J. Sosnowski Warsaw University of Technology |
| 11.20 - 11.40 | Coffee Break |
| 11.40 - 12.40 | Session 2: On-Line Testing for Reconfigurable Systems Moderator: Renato Stefanelli, Politecnico di Milano Coordinator: , |
| 2.1. | On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs C. Stroud, M. Lashinsky, J. Nall, J. Emmert, M. Abramovichi University of North Carolina & Agere Systems |
| 2.2. | DRAFT : An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs M. Gericota, G. Alves, M. Silva, J. Ferreira ISEP & FEUP |
| 2.3. | Testing FPGA Delay Faults in the System Environment is very Different from "Ordinary" Delay Fault Testing A. Krasniewski Warsaw University of Technology |
| 12.40 - 14.00 | Lunch |
| 14.00 - 15.20 | Session 3: Design of On-Line Testable and Fault Tolerant Circuits and Systems Moderator: C.A. Papachristou, Case Western Reserve U. Coordinator: Greg Tollefson, Intel |
| 3.1. | Logic Optimization of Unidirectional Circuits with Structural Methods L. Entrena, C. Lopez, E. Olias, E. San Millan, J. Espejo Universidad Carlos III |
| 3.2. | Automatic Insertion of Fault-Tolerant Structures at the Register Transfer Level L. Entrena, C. Lopez, E. Olias Universidad Carlos III |
| 3.3. | On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity M. Pflanz, K. Walther, H.T. Vierhaus BTU Cottbus |
| 3.4. | Novel Fault - Tolerant Adder Design for FPGA - Based Systems M. Alderighi, S. D' Angelo, C. Metra, R. Sechi Cosmica "G. Occhialini", Consiglio Nazionale delle Ricerche & Universita di Bologna |
| 15.20 - 15.40 | Coffee Break |
| 15.40 - 17.10 | Panel: Yield, Test & Reliability Issues for Very Deep Submicron Chips Organized by: C. Metra U. Bologna & M. Nicolaidis iRoC Technologies Co-organized by: IEEE Design & Test of Computers Moderator: B. Ricco, U. Bologna |
| Panelists: | E. Dupont, iRoC Technologies Y. Zorian, QStar H. Levendel, Motorola R. Kleinhorst, Philips B. Russo, STMicroelectronics |
| 19.30 | - Welcome Dinner - |
Tuesday July 10, 2001. | |
| 08.30 - 09.30 | Session 4: Logic Verification for On-Line Tested Systems Moderator: Paolo Prinetto, Politecnico di Torino Coordinator: , |
| 4.1. | Recent results in logic verification D.K. Pradhan U. Bristol |
| 4.2. | Automatic Bias Generation using Pipeline Instruction State Coverage for Biased Random Instruction Generation M. Bose, E. Rudnick, M. Abadir University of Illinois & Motorola |
| 09.30 - 09.50 | Coffee Break |
| 09.50 - 10.50 | Session 5: Built-In Self Testing Moderator: Davide Appello, STMicroelectronics Coordinator: Kaushik Roy, Purdue U. |
| 5.1. | Using a WLFSR to Embed Test Pattern Pairs in Minimum Time D. Kagaris, S. Tragoudas Southern Illinois University |
| 5.2. | A New Reseeding Technique for LFSR-Based Test Pattern Generation E. Kalligeros, X. Kavousianos, D. Bakalis, D. Nikolos University of Patras & Computer Technology Institute |
| 5.3. | A Gated Clock Scheme for Low Power Scan-Based BIST Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch LIRMM |
| 5.4. | Test-per-Clock Testing of the Circuits with Scan Full O. Novak, J. Nosek Technical University Liberec |
| 10.50 - 11.10 | Coffee Break |
| 11.10 - 12.30 | Session 6: Self Checking, Concurrent Detection & Radiation Effects Moderator: Antonio Imbruglia, STMicroelectronics Coordinator: Hans Manhaeve, Q-Star Test |
| 6.1. | Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers O. Petre, H.G. Kerkhoff University of Twente |
| 6.2. | Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures M. Favalli, C. Metra University of Ferrara & University of Bologna |
| 6.3. | Concurrent Detection of Soft Errors Based on Current Monitoring Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, C. Efstathiou ISD SA, Southern Illinois University, University of Patras & TEI of Athens |
| 6.4. | A New Laser System for X-Rays Flashes Sensitivity Evaluation D. Lewis, H. Lapuyade, Y. Deval, Y. Maidon, F. Darracq, R. Briand, P. Fouillat IXL, U. Bordeaux |
| 12.30 - 13.50 | Lunch |
| 13.50 - 14.50 | Session 7: Automotive Applications & On-Line Monitoring of Temperature Moderator: Ray Mercer, Texas A&M U. Coordinator: George Stamoulis, Technical University of Crete |
| 7.1. | Fault Tolerant Automotive Systems: An Overview A. Manzone, A. Pincetti, D. De Constantini FIAT |
| 7.2. | Smart Temperature Sensor for On-line Monitoring in Automotive Applications J.L. Merino, S.A. Bota, E. Cabruja, X. Jorda, A. Ferre, A. Herms, J. Bausells, J. Bigorra, J. Samitier Universidad de Barcelona, CNM-CSIS & Applied Research-European Technological Centre |
| 7.3. | CMOS Differential and Absolute Thermal Sensors A. Syal, V. Lee, A. Ivanov, J. Altet University of British Columbia & UPC |
| 14.50 - 15.10 | Coffee Break |
| 15.10 - 16.10 | Session 8: Posters Moderator: , Coordinator: , |
| 8.1. | An Approach for Designing On-Line Testable State Machines P.K. Lala, M.G. Karpovsky U. of Arkansas & Boston University |
| 8.2. | Power Constrained Test Scheduling with Low Power Weighted Random Testing X. Zhang, K. Roy Purdue University |
| 8.3. | Designing Reliable Embedded Systems Based on 32 Bit Microprocessors C. Bolchini, F. Salice, D. Sciuto Politecnico di Milano |
| 8.4. | On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation C. Aktouf LCIS - ESISAR |
| 8.5. | Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection M. Boehnel, R. Weiss Graz University of Tecnology |
| 8.6. | A Study of the Experimental Validation of Fault-Tolerant Systems using Different VHDL-Based Fault Injection Techniques J. Gracia, J.C. Baraza, D. Gil, P.J. Gil Universidad Politecnica de Valencia |
| 8.7. | TRACS - TRansient Activity Checking with Scan Cells J. Dos Santos ISEP |
| 8.8. | An On-Line Testing Approach Using Code-Perturbation Z. Yang, G. Choi Texas A&M University |
| 8.9. | Fault Tolerant IC Design by Area-Optimized Error Correcting Codes R. Kleihorst, N. Benschop Philips |
| 8.10. | Totally Self-Checking FSM Design based on Multilevel Synthesis Methods and FPGA Implementation A. Matrosova, K. Nikitin, O. Goloubeva Tomsk State University |
| 16.30 | Social Program (Tour and Gala Dinner). |
Wednesday July 11, 2001 | |
| 08.30 - 09.30 | Session 9: Self Checking Circuits & Error Control Coding Implementation Moderator: Ilya Levin, Tel Aviv U. Coordinator: Donatella Sciuto, Politecnico di Milano |
| 9.1. | Low Code-disjoint Carry-dependent Sum Adder with Partial Look-Ahead V. Otscheretnij, M. Gossel, E.S. Sogomonyan U. of Potsdam |
| 9.2. | On the Design of Self-Testing Checkers for Berger Codes S.J. Piestrak, D. Bakalis, X. Kavousianos Wroclaw University of Technology, University of Patras & Computer Technology Institute |
| 9.3. | Fast Configurable Polynomial Division for Error Control Coding Applications F. Monteiro, A. Dandache, B. Lepley U. of Metz |
| 09.30 - 09.50 | Coffee Break |
| 09.50 - 10.50 | Session 10: Hardware & Software Techniques for Fault Tolerance Moderator: Adelio Salsano, Univ. Roma II Coordinator: Massimo Mastrocola, STMicroelectronics |
| 10.1. | Reliability Properties Assessment at System Level: A Co-design Framework C. Bolchini, L. Pomante, F. Salice, D. Sciuto Politecnico di Milano |
| 10.2. | Effectiveness and Limitations of Various Software Techniques for "soft error" Detection: A Comparative Study B. Nicolescu, R. Velazco, M. Sonza Reorda TIMA & Politecnico di Torino |
| 10.3. | Supporting Fault Tolerance in an Industrial Environment: the AMATISTA Approach I. Gonzalez, L. Berrojo Alcatel Espacio |
| 10.50 - 11.10 | Coffee Break |
| 11.10 - 12.30 | Session 11: Applications Moderator: Flavio Lorenzelli, STMicroelectronics Coordinator: Franco Fummi, University of Verona |
| 11.1. | A New Approach to Design Reliable Real-Time Speech Recognition Systems F. Vargas, R.D. Fagundes, D. Barros Catholic University PUCRS |
| 11.2. | Built In Self Test for Low Cost Testing of a 60 Mhz Synchronous Flash Memory V. Mastrocola, G. Palumbo, P. Kumar, F. Pipitone, G. Introvaia University of Catania & STMicroelectronics |
| 11.3. | Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Control F.M. Goncalves, M.B. Santos, I.C. Teixeira, J.P. Teixeira IST/INESC |
| 11.4. | On-Line Multiple-Fault-Detection of Fuzzy Controllers N. Kamiura, T. Isokawa, N. Matsui, K. Yamato Himeji Institute of Technology & Hyogo University |
| 12.30 - 14.00 | Lunch |
| 14.00 - 15.00 | Session 12: On-Line Testing of Digital, Analog and Mixed Signal Circuits Moderator: Abhijit Chaterjee, Georgia Tech. Univ. Coordinator: Giuseppe Di Gregorio, STMicroelectronics |
| 12.1. | A Robust Fault Detection Scheme for Concurrent Testing of Linear Digital Systems E. Simeu, A. Abdelhay TIMA |
| 12.2. | Single and Double Fault Diagnosis for Linear Analog Circuits with Symbolic Analysis and Reduced Observable Point Set M. Artioli, F. Filippetti Universita degli Studi di Bologna |
| 12.3. | Mixed-Signal Circuit Classification in a Pseudorandom Testing Scheme C. Marzocca, F. Corsi Politecnico di Bari |
Back
IEEE Computer Society
Test Technology TechnicalCouncil