Program Committee

J. Abraham, Univ. Texas at Austin E. Boehl, Robert Bosch GmbH C. Bolchini, Politecnico di Milano A. Dandache, Univ. Metz J. Figueras, U.P. de Catalunya P. Girard, LIRMM D. Gizopoulos, Univ. Piraeus M. Gössel, Univ. of Postdam Th. Haniotakis, Univ. Southern Illinois A. Ivanov, Univ. of Brit. Columbia R. Iyer, Univ. Illinois D. Kagaris, Univ. Southern Illinois R. Kleihorst, Philips A. Krasniewski, Warsaw U.T. K. Kuchukian, Armenian NAS P.K. Lala, Univ. of Arkansas H. Levendel, Motorola I. Levin, Univ. Tel Aviv J.C. Lo, Univ. Rhode Island S. Mitra, Univ. Stanford

Y. Maidon, Univ. Bordeaux H. Manhaeve, QStar A. Orailoglu, Univ. Cal. San Diego A. Paschalis, Univ. Athens S. Piestrak, iRoC Technologies D. Pradhan, Univ. Bristol M. Rebaudengo, Politecnico di Torino K. Roy, Purdue Univ. J. Segura, Univ. Illes Balears E. Simeu, TIMA Laboratory J. Sosnowski, Warsaw U.T. G. Stamoulis, Univ. Crete B. Straube, Fraunhofer IIS/EAS C.E. Stroud, U.N. Carolina at Charlotte N.A. Touba, Univ. Texas at Austin S. Tragoudas, Univ. Southern Illinois Y. Tsiatouhas, ISD F. Vargas, PUCRS H.T. Vierhaus, Brandenburg T.U.

Monday July 8, 2002
07.30 - 08.30	Registration
08.30 - 08.40	Opening Address
08.40 - 09.30	Keynote Address
09.30 - 09.50	Coffee Break
09.50 - 10.50	Session 1: Hardware Fault Tolerance Moderator: J. Abraham, Univ. of Texas at Austin Coordinator: D. Marino, Alstom Transport
1.1.	An Architecture for Self-healing Digital Systems P.K. Lala, B. Kiran Kumar Univ. of Arkansas & Politecnico di Torino
1.2.	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland, C. Metra Univ. of Bologna & Philips Research Laboratories
1.3.	Survivable Discrete Circuits Design A. Matrosova, V. Andreeva, Yu. Sedov Tomsk State Univ.
10.50 - 11.10	Coffee Break
11.10 - 12.10	Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems Moderator: H. Levendel, Motorola, USA Coordinator: M. Alderighi, National Research Council, Italy
2.1.	Fault Tolerance Evaluation Using two Software Based Fault Injection Methods A. Ademaj, P. Grillinger, P. Herout, J. Hlavicka Univ. of Technology of Vienna & Univ. of West Bohemia & Czech Technical Univ.
2.2.	Automated Synthesis of SEU Tolerant Architectures from OO Descriptions S. Chiusano, S. Di Carlo, P. Prinetto Politecnico di Torino
2.3.	A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems C. Bolchini, L. Pomante, F. Salice, D. Sciuto Politecnico di Milano
12.10 - 13.50	Lunch
13.50 - 14.50	Session 3: Self-Cheking Circuits Moderator: D. Gizopoulos, Univ. Pireus, Greece Coordinator: A. Pagni, STMicroelectronics, Italy
3.1.	A New Self-checking Code-disjoint Carry-skip Adder M. Goessel, D. Marienfeld, E.S. Sogomonyan, V. Ocheretnij Univ. of Postdam
3.2.	Sequential Circuits Applicable for Detecting Different Type of Faults I. Levin, V. Sinelnikov, M. Karpovsky, S. Ostanin Univ. of Tel-Aviv & Univ. of Boston
3.3.	Input Ordering in Concurrent Checkers to Reduce Power Consumption N.A. Touba, K. Mohanram Univ. of Texas at Austin
14.50 - 15.10	Coffee Break
15.10 - 16.10	Session 4: Concurrent Error Detection I Moderator: A. Salsano, Univ. Roma II, Italy Coordinator: E. Boehl, Bosch, Germany
4.1.	A High Speed Encoder for Recursive Systematic Convolutive Codes F. Monteiro, A. M'Sir, A. Dandache, B. Lepley LCM/CLOES/SUPE LEC & Univ. of Metz
4.2.	A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing Y. Tsiatouhas, A. Arapoyanni, D. Nikolos, Th. Haniotakis ISD, Univ. of Athens & Univ. of Patras & Univ. of Illinois
4.3.	Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems H. Nguyen, A. Chatterjee Georgia Institute of Technology
16.10 - 16.30	Coffee Break
16.30 - 17.30	Session 5: Concurrent Error Detection II Moderator: D. Sciuto, Politecnico di Milano, Italy Coordinator: B. Riccò, Univ. of Bologna, Italy
5.1.	On-Line Error Detection and Correction in Storage Elements with Cross- Parity Check M. Pflanz, K. Walther, H.T. Vierhaus IBM & Univ. of Cottbus
5.2.	On-line Monitor Design of Finite-State Machines F. Gao, J.P. Hayes Univ. of Michigan
5.3.	A Statistical Sampler for a New On-line Analog Test Method M. Negreiros, L. Carro, A. Susin UFRGS
17.30 - 19.00	Panel: Reliability Issues for Very Deep Submicron ICs Organizers: C. Metra, Univ. Bologna, Italy & M. Sonza Reorda, Politecnico di Torino, Italy Moderator: Y. Zorian, Virage Logic
Panelists:	R. Aitken, Agilent S. Van Dijk, Philips Res. Labs T.M. Mak, Intel Corporation E. Dupont, iRoC Technologies
19.30	- Welcome Dinner -

Tuesday, July 9, 2002
08.30 - 09.30	Session 6: Analog and Mixed Signal Testing and Reliability Moderator: Y. Maidon, Univ. of Bordeaux, France Coordinator: A. Ivanov, Univ. of British Columbia, Canada
6.1.	A SD A/D Converter Insensitive to SEU Effects L. Carro, F.P. Cortes, A. Girardi, A. Suzim UFRGS
6.2.	A BICS for CMOS Opamps by Monitoring theSupply Current Peak J. Font, J. Ginard, E. Isern, M. Roca, J. Segura, E. García Univ. de les Illes Balears
6.3.	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours R. Rodríguez-Montañés, D. Muñoz, L. Balado, J. Figueras Univ. Politechnica de Catalunya
09.30 - 09.45	Coffee Break
09.45 - 10.45	Session 7: Fault Injection Techniques and Results Moderator: F. Vargas, PUCRS, Brasil Coordinator: F. Fummi, Univ. of Verona, Italy
7.1.	Multi-Level Fault Injection Experiments Based on VHDL Descriptions: a Case Study R. Leveugle, K. Hadjiat TIMA
7.2.	Analysis of SEU Effects in a Commercial Pipelined Processor M. Rebaudengo, M. Sonza Reorda, M. Violante Politecnico di Torino
7.3.	Bit Flip Injection in Processor-based Architectures: A Case Study G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco Univ. of Rome Tor Vergata & TIMA
10.45 - 11.00	Coffee Break
11.00 - 12.00	Session 8: BIST Techniques I Moderator: B. Straube, Fraunhofer IIS/EAS, Germany Coordinator: P. Girard, Univ. of Montpellier, France
8.1.	BIST-Based Delay-Fault Testing in FPGAs M. Abramovici, C. Stroud Agere Systems & Univ. of North Carolina at Charlotte
8.2.	Built-In-Self-Test of Analogue Circuits using Optimised Fault Sets and Transient Response Testing D. Taylor, A. Platts, N. Axelos Univ. of Huddersfield
8.3.	A low power pseudo-random BIST technique N.Z.Basturkmen, S.M. Reddy, I. Pomeranz Univ. of Iowa, Purdue Univ.
12.00 - 13.30	Lunch
13.30 - 14.30	Session 9: BIST Techniques II Moderator: J.P. Teixeira, IST/INESC, Portugal Coordinator: P. Fouillat, Univ. of Bordeaux, France
9.1.	Stop & Go BIST I. Polian, B. Becker Albert-Ludwigs Univ.
9.2.	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register G. Dimitrakopoulos, D. Nikolos, D. Bakalis Univ. of Patras & Computer Technology Institute
9.3.	Built-In Generation of M-sequences with Irreducibles Characteristic Polynomial D. Kagaris Univ. of Southern Illinois
14.30 - 14.45	Coffee Break
14.45 - 15.45	Session 10: Testing Issues Moderator: J. Figueras, UPC, Spain Coordinator: I. Teixeira, IST/INESC, Portugal
10.1.	Active Replication: Towards a Truly SRAM-based FPGA On-Line Concurrent Testing M.G. Gericota, G.R. Alves, M.L. Silva, J.M. Ferreira ISEP & FEUP
10.2.	Stimuli Generation for Behavioral VHDL Descriptions J.F. Santucci, C. Paoli, M.L. Nivet, A. Campana Univ. of Corsica
10.3.	Checkers for RFMatching Networks on an Automatic Test Board B. Russo, G. Di Gregorio, M.G. La Rosa STMicroelectronics
15.45 - 16.45	Session 11: Posters Moderator: K. Roy, Purdue Univ., USA Coordinator: D. Pradhan, Univ. Bristol, UK
11.1.	Adaptive IDDQ: How to Set an IDDQ Limit for Any Device Under Test C. Dallavalle STMicroelectronics
11.2.	On-line Detection and Compensation of Transient Errors in Processor Pipeline-Strucures C. Galke, M. Pflanz, H.T. Vierhaus Univ. of Cottbus & IBM
11.3.	Recovering Sequential Circuits from Temporary Faults: The survival capability of Scan-Cells J.M. Vieira dos Santos ISEP
11.4.	Learning-Based On-Line Testing in Feedforward Neural Networks N. Kamiura, K. Yamato, T. Isokawa, N. Matsui Himeji Institute of Technology & Hyogo Univ.
11.5.	On-line Short-circuits Detection in Digital Devices and Systems A. Kristof Univ. of Technology in Gliwice
11.6.	Using Concurrent and Semi-concurrent On-line Testing During High Level Synthesis: An Adaptable Approach M.A. Naal, E. Simeu, C. Aktouf TIMA & ESISAR/INPG
11.7.	Transformation Based Insertion of On-line Testing Resources in a High-Level Synthesis Environment P. Oikonomakos, M. Zwolinski Univ. of Southampton
11.8.	Robust Data Compression for Analogue Test Outputs A. Rankov, G.E. Taylor, J. Webster Leeds Metropolitan Univ.
11.9.	A New On-Line Robust Approach to Design Noise-Immunr Speech Recognition Systems F. Vargas, R.D.R. Fagundes, D. Barros Jr. PUCRS
11.10.	Radiation Effects Facility RADEF A. Virtanen Univ. of Jyväskylä
11.11.	Sequential n-Detection Criteria: Keep It Simple! I. Polian, M. Keim, N. Mallig, B. Becker Albert-Ludwigs Univ. & Mentor Graphics
11.12.	On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology C. Aktouf, B. Pannetier, P. Lemaître-Auger, S. Tedjini ESISAR/INPG
11.13.	An off-chip sensor circuit for On-Line transient current testing B. Alorda, A. Ivanov, J. Segura Univ. de les Illes Balears & Univ. of British Columbia
11.14.	Analyses of the Equivalences and Dominancies of Transient Faults at the Register Transfer Level C. Lopez, L. Berrojo, F. Corno, L. Entrena, I. González, M. Sonza Reorda, G. Squillero Univ. Carlos III de Madrid & Alcatel Espacio & Politecnico di Torino
11.15.	Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller F. Lima, L. Carro, R. Velazco, R. Reis UFRGS & TIMA
11.16.	Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach F. Kaddour, S. Rezgui, R. Velazco, S. Rodriguez, J.R. De Mingo TIMA & INTA
17.10	- Social Event (Tour and Gala Dinner) -

Wednesday July 10, 2002 Joint IOLT-MTDT Program
08.45 - 09.30	Session 12: Keynote Address Adam Kablanian, Chairman of the Board, President and CEO, Virage Logic, Inc. Topic: Embedded Memory Test and Repair
09.30 - 10.00	Coffee Break
10.00 - 11.00	Session 13: Memory BIST Analysis and Application Moderator: B. Courtois, TIMA, France
13.1.	Defect-Oriented Analysis of Memory BIST Tests A. Jee HPL, Inc.
13.2.	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda STMicroelectronics & Politecnico di Torino
13.3.	A Scan-BIST Environment for Testing Embedded Memories F. Lombardi, F. Karimi Northeastern University
11.00 - 11.15	Coffee Break
11.15 - 12.15	Session 14: Memory ECC and Soft Errors Moderator: C. Hawkins, Univ. Albuquerque, USA
14.1.	Soft Error Protection for Embedded Memories M. Nicolaidis iRoC Technologies
14.2.	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memory D. Rossi, C. Metra, B. Riccò Univ. of Bologna
14.3.	High-Speed 15ns 4Mbit SRAM for Space Applications B. Coloma, P. Delaunay, O. Husson Atmel
12.15 - 13.45	Lunch
13.45 - 14.45	Session 15: High Reliability in Railway and Automotive Systems Moderator: R. Kleihorst, Philips Research Labs, The Netherlands Coordinator: S. D'Angelo, National Research Council, Italy
15.1.	The YATE fail-safe interface: the user's point of view D. Bied-Charreton, D. Guillon, B. Jacques INRETS & Technicatome & CSEE Transport
15.2.	Fault Tolerant Insertion And Verification: A Case Study A. Manzone, D. De Costantini Centro Ricerche FIAT
15.3.	Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems L. Schiano, C. Metra Univ. of Bologna
14.45 - 15.00	Coffee Break
15.00 - 16.00	Session 16: Embedded Memory Yield Enhancement Moderator: ,
16.1.	A Silicon-Based Yield Gain Evaluation Methodlogy for Embedded-SRAMs with Different Redundancy Scenarios E. Rondey, Y. Tellier, S. Borri Altis Semiconductor & Infineon Technologies
16.2.	A March-Based Fault Location Algorithm for Static Random Access memories V.A. Vardanian, Y. Zorian Virage Logic Inc.
16.3.	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories R-F. Huang, J-F. Li, J-C. Yeh, C-W. Wu National Tsing Hua Univ.
16.00	Closing of Joint IOLT-MTDT Program

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Test Technology Technical Council