1st IEEE International On-Line Testing Workshop

July 4-6, 1995

General Chair                    Program Chair
        
M. Nicolaidis,TIMA               D. Pradhan, Texas A&M U.

Vice-General Chair               Local Arrangements

Y. Zorian, AT&T Bell Labs        B. Rouzeyre, LIRMM

Publicity                        ETTTC Liaison

R. Velazco, INPG/LGI             C. Landrault, LIRMM

                        Program Committee

J. A. Abraham, U. of Texas              F. Lombardi, Texas A&M U.

E. Boehl, Robert Bosch GmbH             L. Grobelny, Zentrum Mikroelektronik Dresden

B. Bose, Oregon State U.                E. J. McCluskey, Stanford U.

J. Bruck, Cal Tech                      T. Nanya, Tokyo Inst. of Techn.

D. C. Bossen, IBM                       A. Osseiran, EPFL

W. Debaney, Rome Lab. RL/ERDA           A. Paschalis, NCSR Demokritos

A. Fernandes, UFMG, Brazil              S. J. Piestrak, Wroclaw Techn. U.

J. Figueras, U. Polit. de Catalunya     P. Prinetto, Politecnico di Torino

M. Goessel, Max-Plank Society           T.R.N. Rao, U. SW Louisiana

S. Gupta, USC                           S. M. Reddy, Iowa U.

N. Jha, Princeton U.                    F. Simon, Alcatel Alsthom Rech.

M. G. Karpovsky, Boston U.              A. D. Singh, Auburn U.

O. Kebichi, TIMA                        E. S. Sogomonyan, Russian

K. Kuchukian, Armenian NAS              Academy of Science

P.K. Lala, N. Carolina A&T State U. U. Sparman, U. of Saarlandes,

R. Leveugle, INPG/CSI                   J. Stiffler, Sequoia Systems

J. C. Lo, Rhode Island U.

The increased complexity of electronic systems has seen increasing reliability needs in various application domains as well as pressure for low cost products. There is a corresponding increased demand for cost-effective on-line test techniques. This workshop will create a forum to discuss all aspects of on-line testing and enhance the links between researchers working in various domains such as VLSI Testing, defect analysis in standard and hostile environments, sensing of reliability relevant indicators, on-line testing, concurrent checking, fail-safe and fault-tolerant design, etc. and system developers concerned with reliability sensitive applications such as avionics, satellites, automotive, railways, medical electronics, industrial control ...

The goal is to stimulate cross-fertilisation in these disciplines on directions sensitive to influence the design of next generation electronic systems.

52 technical papers reflecting most of these domains was selected for the final program.

To be held annually at different sites, the Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee, co-organized by TTTC On-line Testing Technical Activity Committee and the European Test Technology Technical Committee (ETTTC).

7:00 - 8:15 Registration

8:15 - 8:30 Welcome address

8:30-10:10

Session 1: Self-Checking and Fail-Safe Designs

Moderator : B. Kaminska, Ecole Polytechnique de Montréal

1.1 Reconfigurable CPU Cache Memory Design Fault Tolerance and Performance Evaluation, D. Nikolos, H.T. Vergos, T. Mitsiadis, University of Patras

1.2 CAD of Fail Safe Compliant AISCs, A. Dandache, H. Berviller, F. Monteiro, B. Lepley, Metz University

1.3 Experiences in the Design of a CPU with On-Line Self-Test, E. Bohl, Robert, Bosch GmbH

1.4 Safety Computations in Integrated Circuits, J. Dufour, Matra Transport

1.5 Programmable Self-Checking Analogue Oscilators, S. Mir, M. Lubaszewski, V. Kolarik, B. Courtois, TIMA

10:10-10:30 Coffee Break

10:30 - 12:10

Session 2: System Level On-Line Testing

Moderator : R. Leveugle, CSI/INPG, Grenoble

2.1 Hierarchical Distributed Diagnosis of Parallel Message-passing Machines, C. Aktouf, O. Benkahla, C. Robach, LGI-IMAG

2.2 Witness Approach to Concurrent Error Detection in Multiprocessor Systems, A. Sengupta, C.S. Raghavendra, Washington State University

2.3 On Test Strategy Planning for the Self-Checking Circuits, S.L. Frenkel, Inst. of Informatics Problems Russian Academy of Science

2.4 Evaluation of Software for Detecting Hardware Faults, S.Gerber, Max Planck Society, D. R. Avresky, Texas A&M University

2.5 A System Level On-Line Testing Approach, N. Suri, Allied Signal

12:10-13:30 Lunch

13:30 - 14:50

Session 3: On-Line Testing in Space Applications

Moderator : J.Y. Le Gall, Alcatel Espace

3.1 On Chip Dosimeter Compatible Digital CMOS, E. Garcia-Moreno, B. Iniguez, M. Roca, J. Sequra, S. Sureda, Univ. of Illes Balears

3.2 Design of MCMs for Space Radiation Environments Based on Current Monitoring, F. Vargas, M. Nicolaidis TIMA, Y. Zorian, AT&T Bell Labs.

3.3 On-Line Testing a Complex Space System, M.P. Kluth, Alcatel Alsthom Recherche, F. Simon, Alcatel Alsthom Recherche, J. LeGall, Alcatel Espace

3.4 Robustness of Hardware Implementations of Artificial Neural Networks: A Case Studied, A. Assoum, N.E. Radi, R. Velazco, LGI/IMAG, J.M. Torres Moreno, M.B. Gordon, CEA Grenoble, R. Eccofet, CNES Toulouse

14:50 - 15:20 Coffee Break

15:20 - 17:00

Session 4: BIST

Moderator : T.W. Williams, IBM, Microelectronics Division

4.1 No-Overhead BIST for FPGAs, M. Abramovici, AT&T Bell Labs, C. Stroud, University of Kentucky

4.2 Analysis of Accumulator-Based Compaction of Test Responses, K. Chakrabarty, J. Hayes, University of Michigan

4.3 High Level Synthesis of Self-Testable VLSI Designs, I. Harris, M. Vahidi, A. Orailoglu, University of California

4.4 Test Sequences Embedding with Cellular Automata, F. Fummi, D. Sciuto, Polilecnico di Milano, M. Serra, University of Victoria

4.5 On Generation of Prescribed Set of Test Vectors, R. Latypov, Kazan, State University

17:00 - 17:20 Coffee Break

17:20 - 18:20

Panel Session

Moderator : D. Pradhan, Texas A&M University

20:30 - Dinner

Wednesday, July 5, 1995

8:30 - 10:10

Session 5: Concurrent Checking

Moderator : Y. Zorian AT&T Bell Labs

5.1 Synthesis of Online Testable Circuits, D.K. Pradhan, Texas A&M University

5.2 SFS Berger Encoded 2's Complement Modified Booth Array Multipliers with Wallace Tree, J.C. Lo, University of Rhode Island

5.3 Automatic Synthesis of Fault Secure Circuits, T. Markas, E. Edwards, N. Kanopoulos, Research Triangle Institute

5.4 Control Flow Checking in FSMs: Sequencing Error Detection, Efficiency Study, R. Rochet, R. Leveugle, G. Saucier, INPG/CSI

5.5 ROM-Based Synthesis of Large Controllers with Control Flow Checking Capabilities, X. Wendling, V. Sornette, L. Leveugle, INPG/CSI

10:10 - 10:30 Coffee Break

10:30 - 12:30

Session 6: Checking Reliability Indicators

Moderator : B. Courtois, TIMA, Grenoble

6.1 Novel Method for On-Line Thermal Monitoring of Electronic Systems, V. Szekely, Z. Benedek, Z. Kohari, C. Marta, M. Rencz, Technical University of Budapest

6.2 Built-in Crosstalk Safety Margin Testing, E. Sicard, J.Y. Fourniols, INSA, C. Garres, Matra Marconi Space

6.3 A Global Current Testing Approach, M. Nicolaidis, T. Calin, F. Vargas, TIMA

6.4 IDDQ Monitoring for On-Line Detection of Transient and Delay Faults in Self-Checking CMOS Circuits, A. Singh, Auburn University

6.5 Current Untestable Irredundant Bridging Defects in CMOS Static Memory Cells, R. Rodriguez-Montanes, J. Figueras, Universitat Politecnica de Catalunya

6.6 Designing of Self-Checking FSMs within Industrial Design Environments, F. Corno, P. Prinetto, M. Reorda, Politechico di Torino

12:30 - 13:30 Lunch

13:30Social Event: Excursion to Iles de Lérins, Dinner at Cannes

Thursday, July 6, 1995

8:30 - 10:10

Session 7 : BIST/DFT

Moderator : H.J. Wunderlich, Siegen Univeristy

7.1 Partial Scan Insertion Tool for Highly Sequential Digital Circuits, M.A. Allende, F.J. Llacer, M. Martinez, S. Bracho, E.T.S.I. Industries u de Telecommunicacion

7.2 Design for Testability for Asynchronous Devices, L. Grobelny, Zentrum Mikroelektronik Dresden

7.3 Enhancing Fault Coverage of Pseudo-exhaustive Test Sets, O. Novak, Technical University Liberec, J. Hlavicka, Czech Technical University

7.4 Comparisons of Hardware Test Pattern Generators and Extension to Delay Fault Test Sequences, C. Dufaza, H. Viallon, LIRMM

7.5 Quantitative Measures of Pseudorandom BIST Generators and the Improvement of Delay Fault Coverage, S. Zhang, D.M. Miller, J.C. Muzio, University of Victoria

10:10 - 10:30 Coffee Break

10:30 - 11:50

Session 8: Mixing On-Line/Off-Line Testing

Moderator : J.P. Hayes, Michigan University

8.1 Concurrent Testing of Latent Modules in Synthesized Systems, K. Baker, M. Zwolinski, A. Brown, University of Southampton

8.2 Memory Test Architecture in a Telecommunication System, S. Barbagallo, Italtel, Settimo Milanese, F. Corno, P. Prinetto, M. Reorda, Politecnico di Torino

8.3 A New Parity-Preserving Multi Input Signature Analyzer, E. Sogomonyan, M. Goessel, Max-Planck Society

8.4 Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability, S. Tarnick, Max-Planck Society

11:50 - 13:20 Lunch

13:20 - 14:40

Session 9: Self-Checking Checkers

Moderator : M. Goessel, Max Planck Society

9.1 Efficient Structured Design of Robustly Testable CMOS TSC M-out-of-2M Code Checkers, A. Paschalis, Th. Haniotakis, NCSR "Democritos"

9.2 Efficient Self-Checking checkers for Berger Codes, P. Lala, D. Pierce, North Carolina Agricultural & Technical State University

9.3 A Totally Self Checking Reconfigurable N-Modular Redundancy System with Separate Internal Fault Indication, N. Gaitanis, NCSR "Demokritos"

9.4 Highly Testable 1-out-of-n Dynamic CMOS Checker, C. Metra, M. Favalli, B. Ricco, D.E.I.S. Universita di Bologna

REGISTRATION: The early registration fee is 1800 FF. This includes, lunches, coffee breaks and the social event. Early registration is by June 10th. Late registration fee is 2.000 FF. To be sent to:

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