Preliminary Program

           IEEE Computer Society Test Technology Technical Committee

General Chairs M. Nicolaidis, TIMA Lab. M. Sonza Reorda, Polit. di Torino	Program Chairs J. Abraham, U. of Texas at Austin D. Nikolos, U. Patras
Vice-General Chair Y. Zorian, LogicVision	Vice-Program Chairs C. Metra, DEIS - U. di Bologna D. Pradhan, Texas A&M U.
Local Arrangements F. Corno, Polit. di Torino
Financial Chair M. Rebaudengo, Polit. di Torino
Secretariat V. Mazzanti, Polit. di Torino	ETTTC Liaison C. Landrault, LIRMM

Program Committee

M. Abramovici, Lucent Technologies L. Alkalai, JPL/Caltech S. P. Athan, U. South Florida E. Boehl, Robert Bosch GmbH S. Bracho, U. of Cantabria W. Debaney, Rome Lab. RL/ERDA C. Dufaza, LIRMM J. Figueras, U. P. de Catalunya P. Prinetto, Politecnico di Torino W. K. Fuchs, Purdue U. M. Goessel, Potsdam U. J. P. Hayes, U. of Michigan S. Hellebrand, U. of Siegen L. Impagliazzo, Ansaldo A. Ivanov, U. of Brit. Columbia R. Iyer, U. Illinois B. Kaminska, OPMAXX N. Kanopoulos, DCT R. Karri, Lucent Technologies K. Kuchukian, Armenian NAS

P. K. Lala, N. Carolina A&T State U. H. Levendel, Lucent Technologies R. Leveugle, CSI/INPG J. C. Lo, Rhode Island U. P. Marchal, CSEM SA E. J. McCluskey, Stanford U. D. Medina, Italtel V. S. S. Nair, South. Methodist U. T. Nanya, Tokyo Inst. of Techn. A. Orailoglu, U. of Cal. San Diego A. Paschalis, NCSR Demokritos S. Piestrak, Wroclaw U. of Techn. A. D. Singh, Auburn U. E. S. Sogomonyan, Rus. A. of Sc. C. E. Stroud, U. Kentucky V. Szekely, TU of Budapest F. Vargas, PUCRS R. Velazco, TIMA Lab. H. J. Wunderlich, U. of Stuttgart

8.30 - 9.00 Opening Address

9.00 - 10.40 Session 1: System Level Reliability
Moderator : J. P. Hayes, U. of Michigan
1.1 Speculation-Based Distributed Simulation for Dependability Analysis: A Case Study, Y. Huang, Z. Kalbarczyk, R. K. Iyer, Univ of Illinois at Urbana-Champaign
1.2 Linear Codes for Error Correction (LEC), V. S. S. Nair, Z. Alkhalifa, Southern Methodist Univ.
1.3 Testing a K-Ary N-Cube Interconnection Network, S. Kumarasamy, S. K. Gupta, M. A. Breuer, Univ. Southern California
1.4 Reliability-Oriented HW/SW Partitioning Approach, F. Vargas, E. Bezerra, L. Wulff, D. B. Junior, Catholic Univ.-PUCRS

10.40 - 11.00 Break

11.00 - 12.15 Session 2: Case Studies
Moderator : M. A. Breuer, U. Southern California
2.1 Flight Results Analysis of Digital Experiment Devoted to Satellite Image Processing by Means of Neural Nets, Ph. Cheynet, R. Velazco, TIMA Lab., R. Ecoffet, CNES-CT/AQ/CE, S. Buchner, SFA INC
2.2 Emulation Based Real Time Testing of Automotive Applications, J. Abke, Univ. Hanover, E. Boehl, C. Henno, Robert Bosch GmbH
2.3 Intelligent Field Test and Diagnosis: A Case Study, I. Beniaminy, IET Intellligent Electronics, E. Greenberg, EI-Op.

12.15 - 13.30 Lunch

13.30 - 15.10 Session 3: Off-Line and On-Line Self-Test
Moderator : Y. Zorian, LogicVision
3.1 Built-In Self-Test of FPGA Interconnect, C. Stroud, S. Wijesuriya, C. Hamilton , Univ. Kentuky, M. Abramovici, Bell Labs.
3.2 Utilizing Off-line BIST Circuitry for the On-line Test of Finite State Machines, A. Hertwig, S. N. Hamilton, Univ Stuttgart, A. Orailoglu, Univ. California , San Diego
3.3 Maximizing the Effectiveness of On-Line Testing Functions, C. Stroud, M. H. Ding, W. K. Long, Y. Yang, Univ. Kentuky, R. Karri, S. L. Wu, Lucent Technologies
3.4 A SCAN Based Concurrent BIST Approach for Low-Cost On-Line Testing, E. S. Sogomonyan, Russian Academy of Sciences, A. D. Singh, Auburn Univ., M. Goessel, Potsdam Univ.

15.10 - 15.30 Break

15.30 - 16.45 Session 4: Current Monitoring
Moderator : D. Bhattacharya, DSP R&D Center, Texas Instr.
4.1 Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS, T. Calin, L. Anghel, M. Nicolaidis, TIMA Lab.
4.2 A Low-Voltage, Built-in Current Sensor for Digital CMOS VLSI Testing, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, Univ. Athens
4.3 On-Line Testing of CMOS Circuits Using Idd Waveform Analysis, H. Soeleman, D. Somasekhar, K. Muhammad, K. Roy, Purdue Univ.

16.45 - 17.05 Break

17.05 - 18.20 Session 5: Concurrent Error Detection
Moderator : M. Goessel, Univ. of Potsdam
5.1 A New Scheme for Off-Line and On-Line Testing with ABC and Berger Encoding, O. Potin, C. Dufaza, C. Landrault, Univ. Montpellier II
5.2 On Concurrent Testing of DSP-Based Architectures, C. Aktouf, O. Minez, C. Robach, LCIS-ESISAR
5.3 The Impact of Logic Optimization on Concurrent Error Detection, VI. Moshanin, V. Ocheretnij, A. Dmitriev, Univ. Potsdam

8.30 - 10.10 Session 6: BIST
Moderator : C. Landrault, LIRMM
6.1 Further Results on LOT: Logic Optimisation for Random BIST Testability Improvement, M. Chatterjee, D. Pradhan, W. Kunz, Stanford Univ.
6.2 Exhaustive and Pseudoexhaustive Arithmetic Built-In Two-Pattern Generation for Datapaths, I. Voyiatzis, A. Paschalis, NCSR Democritos, D. Nikolos, Univ. Patras, C. Halatsis, Univ. Athens
6.3 BIST TPG for Functionally Sensitizable and Singly Testable Path Delay Faults, D. Kagaris, S. Tragoudas, Southern Illinois Univ.
6.4 Behavioral Test Generation for Test Embedding, F. Ferrandi, F. Fummi, D. Sciuto, Politecnico di Milano

10.10 - 10.30 Break

10.30 - 12.10 Session 7: Radiation Issues
Organizer & Moderator : R. Velazco, TIMA Lab.
7.1 Elaboration of a New Pulsed Laser System for SEE Testing, V. Pouget, H. Lapuyade, D. Lewis, P. Fouillat, Y. Maidon, L. Sarger, Univ. Bordeaux, T. Calin, R. Velazco, TIMA Lab.
7.2 A Testable Fault-Tolerant VLSI Digital Filter for the FERMI Readout Microsystem, R. Mariani, S. Motto, C.A.E.N Microelettronica, M. Ljuggren, Univ. Stockholm, R. Benetta, H. Magnus, CERN
7.3 Radiation-Tolerant On-Line Monitoring MAC Unit for Neural Models Using Reconfigurable Logic FIPSOC Devices, J. Madrenas, J. M. Moreno, J. Cabestany, Univ. Politecnica de Catalunya, J. Faura, J. M. Insenser, SIDSA
7.4 Modelling Radiation Effects on Bipolar Transistors with SPICE, E. Arcauz, S. Coenen, M. Decreton, SCK-CEN Belgium

12.10 - 13.30 Lunch

13.30 - 15.10 Session 8: Fault Tolerant and Fail Safe Systems
Moderator : P. K. Lala, U. South Florida
8.1 Fault-Tolerant Self-Dual Circuits with Error Detection by Parity and Group Parity Prediction, V. Ocheretnij, M. Goessel, Univ. of Potsdam, VI. V. Saposhnikov, V. V. Saposhnikov, Railway Transportation State Univ.
8.2 XMR: The Incomplete TMR Solution, J. M. V. dos Santos, ISEP-I.S. Eng. Porto, J. M. M. Ferreira, FEUP-Univ. Porto.
8.3 Rules for the Design of Fail-Safe Circuits in Transportation Systems, D. Bied-Charreton, INRETS-ESTAS
8.4 A Secure Interface Based on BIST and Hybrid Coding Techniques, F. Monteiro, A. Dandache, H. Berviller, B. Lepley, Univ. Metz

16.00 Social Event

8.30 - 10-10 Session 9: Self-Checking Data Paths and Controllers
Moderator : J. Figueras, U. P. de Catalunya
9.1 A CAD Framework for Generating Self-Checking Multipliers Using Residue Arithmetic Codes, I. Alzaher, M. Nicolaidis, TIMA Lab.
9.2 On-Line Self-Checking of Microprogram Control Units, I. Levin, Tel Aviv Univ., M. Karpovsky, Boston Univ.
9.3 RT-Level Testability Estimation for On-Line Test of Transient Faults, S. Chiusano, F. Corno, M. Sonza Reorda, R. Vietti, Politecnico di Torino
9.4 Self-Checking Synchronous FSM Network Design, A. Yu. Matrosova, S. A. Ostanin, Tomsk State Univ.

10.10 - 10.30 Break

10.30 - 12.10 Session 10: Self-Checking Checkers
Moderator : M. Lubaszewski, DELET/UFRGS
10.1 Novel Implementation of Highly Testable Parity Code Checkers, C. Metra, M. Favalli, B. Ricco, DEIS-Univ. Bologna
10.2 Novel TSC Checkers for Bose-Lin Codes, X. Kavousianos, CTI-Patra , D. Nikolos, Univ. Patras
10.3 General Design Method for VLSI High Speed Berger Code, C. Metra, DEIS-Univ. Bologna, J. C. Lo, Univ. Rhode Island
10.4 General Procedure of Self-Testing Checkers for All M-Out-Of-N Codes with M>3 Using Parallel Counters, S. J. Piestrak, Wroclaw Univ. of Technology

12.10 - 13.30 Lunch

13.30 - 14.45 Session 11: Sensors and Detectors for On-Line Testing
Moderator : B. Kaminska, OPMAXX
11.1 On-Line Testing of Opamp Circuits Using Built-In Detector Observer, J. Velasco Medina, M. Nicolaidis, TIMA Lab., M. Lubaszewski, DELET/UFRGS
11.2 Advanced Sensing Methods for Testing Core-Based Architectures, S. P. Athan, Univ. South Florida, J. L. Kurtz, J. Cowdery, Univ. of Florida
11.3 Residue Checking Method for Concurrent Fault Detection in Linear Analog Systems, E. Simeu, TIMA Lab.

14.45 - 15.05 Break

15.05 - 16.45 Session 12: On-Line Testing Techniques
Moderator : K. Roy, Purdue Univ.
12.1 On-Line Periodic Test Strategy Dedicated to Parallel Computers, F. Clermidy, T. Collette, CEA-LETI
12.2 An Evaluation of Software Redundancy Techniques for Errors Detection, M. Rebaudengo, M. Sonza Reorda, Politecnico di Torino
12.3 On-Line Testing Considerations During the Synthesis of Scalable Signal Processing Architectures, C. Aktouf, G. Al-Hayek, C. Robach, LCIS-ESISAR
12.4 Testing the On-Line Testing Software, A. M. Amendola, L. Impagliazzo, P. Marmo, F. Poli, Ansaldo Segnalamento Ferroviario