IOLTW'99

July 5-7
Rhodes
GREECE

5th IEEE International On-Line Testing Workshop


Preliminary Program

           IEEE Computer Society Test Technology Technical Committee

 

General Chairs
M. Nicolaidis, TIMA Laboratory
A. Paschalis, U. of Athens 		Program Chairs
J. Abraham, U. of Texas at Austin
D. Nikolos, U. Patras
Vice-General Chair
Y. Zorian, LogicVision 		Vice-Program Chairs
C. Metra, DEIS - U. di Bologna
D. Pradhan, Texas A&M U.
Local Arrangements
C. Halatsis, U. of Athens 		Publicity
H. Vergos, U. of Patras
Financial Chair
D. Gizopoulos, 4Plus 		Publications
G. Alexiou, U. of Patras
Secretariat
N. Alonistioti, NCSR Demokritos 		ETTTC Liaison
C. Landrault, LIRMM

Program Committee
M. Abramovici, Lucent Technologies
L. Alkalai, JPL/Caltech
S. P. Athan, U. South Florida
E. Boehl, Robert Bosch GmbH
S. Bracho, U. of Cantabria
C. Dufaza, LIRMM
J. Figueras, U. P. de Catalunya
W. K. Fuchs, Purdue U.
M. Goessel, Potsdam U.
Th. Haniotakis, ISD S.A
J. P. Hayes, U. of Michigan
S. Hellebrand, U. of Siegen
L. Impagliazzo, Ansaldo Trasporti
A. Ivanov, U. of Brit. Columbia
R. Iyer, U. Illinois
B. Kaminska, OPMAXX
R. Karri, Polytechnic U.
K. Kuchukian, Armenian NAS
D. Kagaris, Southern Illinois U.
P. K. Lala, N. Carolina A&T State U. 		H. Levendel, Lucent Technologies
R. Leveugle, CSI/INPG
J. C. Lo, Rhode Island U.
E. J. McCluskey, Stanford U.
D. Medina, HP
V. S. S. Nair, South. Methodist U.
T. Nanya, Tokyo Inst. of Techn.
A. Orailoglu, U. of Cal. San Diego
S. Piestrak, Wroclaw U. of Techn.
P. Prinetto, Politecnico di Torino
A. D. Singh, Auburn U.
E. S. Sogomonyan, Rus. A. of Sc.
M. Sonza Reorda, Pol. Torino
C. E. Stroud, U. Kentucky
E. Simeu, TIMA Laboratory
V. Szekely, TU of Budapest
F. Vargas, PUCRS
R. Velazco, TIMA Laboratory
H. J. Wunderlich, U. of Stuttgart

Monday July 5, 1999

7.30 - 8.30 Registration

8.30 - 9.00 Opening Address

9.00 - 10.40 Session 1. On-Line Testing for FPGAs
Moderator: J. Abraham, U. of Texas at Austin

1.1 - Using Roving STARs for On-Line Testing and Diagnosis of FPGA in Fault-Tolerant Applications, M. Abramovichi, C. Stroud, V. Verma, Lucent Technologies & U. Kentucky
1.2 - Periodic Testing of FPGAs Using a Software Test Method, O-E-K. Benkahla, A. Chauche, C. Aktouf, C. Robach, LCIS/INPG
1.3 - Totally Self-Checking FPGA-based FSM, I. Levin, A. Yu. Matrosova, V. Sinelnikov, S. A. Ostanin, U. of Tel Aviv & Tomsk State U. 10.00 - 10.20 Break

10.20 - 11.20 Session 2. System Level On - Line Testing I
Moderator: F. Vargas, PUCRS

2.1 - Flig A Multi-level Layered System Approach to On-Line Testing, I. Levendel, Motorola
2.2 - On-Line Test Based on Distributed Monitoring, Peng Cheng-Lian, Fudan U.
2.3 - On-Line Testing of Embedded Architectures Using the Idle Computations and Clock Cycles, C. Aktouf, C. Robach, U. Kac, F. Novak, LCIS/ESISAR & Jozef Stefan Inst. 11.20 - 11.40 Break

11.40 - 12.40 Session 3. On-Line Testing and Fault Tolerance Approaches
Moderator: C. Dufaza, LIRMM

3.1 - Combined On-Line/Off-Line Test Solutions for Digital Filters, I. Bayaktaroglu, A. Orailoglu, U. of California, San Diego
3.2 - Real Time Effect Testing of Processor Faults, E. Bohl, W. Harter, M. Trunzer, R. Bosch GmbH
3.3 - Low Performance Degradation Transient Fault Recovery for TMR Systems, C. Metra, S. D'Angelo, G. Sechi, U. of Bologna 12.40 - 14.00 Lunch

14.00 - 14.40 Embedded Tutorial
Radiation Effects in ICs, J. Gasiot, U. of Montpellier II.

14.40 - 15.00 Break

15.00 - 16.00 Session 4. On-Line Testing for nanometer technologies
Moderator: R. Velaszo, TIMA Laboratory

4.1 - Register Transfer Level Approaches to On-Line Testing: An Overview, R. Karri, N. Mukherjee, T. J. Chakraborty, Polytechnic U., Mentor Graphic & Lucent Technologies
4.2 - Implementation and Evaluation of a Soft Error Detecting Technique, L. Anghel, M. Nicolaidis, TIMA Laboratory
4.3 - Concurrent Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults, C. Metra, R. Degiampietro, M. Favalli, B. Ricco, U. di Bologna 16.00 - 16.20 Break

16.20 - 17.40 Session 5. BIST & Low Power
Moderator: C. Papachristou, Case Western Reserve U.

5.1 - Weighted Random Patterns for BIST Generated in Cellular Automata, O. Novak, TU. Liberec
5.2 - More Candidate Polynomials for Pseudo-Exhaustive TPG, D. Kagaris, S. Tragoudas, South Illinois U. & U. of Arizona
5.3 - Design and Synthesis of Programmable Low Power Weighted Random Pattern Generator, X. Zhang, K. Roy, U. of Purdue
5.4 - On Low Power BIST for Carry Save Array Multipliers, D. Bakalis, D. Nikolos, U. of Patras 17.40 - 18.00 Break

18.00 - 19.30 Panel Session. On-Line Testin in The Continuous Operation of Large Systems
Organizer: M. Nicolaidis, TIMA Laboratory
Moderator: Y. Zorian, LogicVision
Panelists:

H. Levendel, Motorola
T.J. Chakraborty, Lucent Technologies
TBD
TBD 20.15 - 22.00 Welcome Reception


Tuesday, July 6, 1999

8.30 - 9.30 Session 6. BIST and Boundary Scan
Moderator: R. Karri, Polytechnic U.

6.1 - Built - in Self - Test for Shifter / ALU Pairs in Datapaths, N. Kranitis, M. Psarakis, A. Paschalis, D. Gizopoulos, Y. Zorian, NCSR Demokritos, 4Plus & LogicVision
6.2 - On Improving 1149.1 BST Reliability for On-Line Scan, J.M. Vieira dos Santos, J.M. Martins Ferreira, U. of Porto
6.3 - A Boundary Scan Based One Channel Timing Analyser, G. Ribeiro Alves, J.M. Martins Ferreira, U. of Porto 9.30 - 9.50 Break

9.50 - 11.10 Session 7. Radiation Issues
Organizer: R. Velazco, TIMA Laboratory
Moderator: J. Hayes, U. of Michigan

7.1 - One Year S.E.U Flight Results for two 32 KB Commercial SRAMs On-Board A Scientific Satelite, Ph. Cheynet, R. Velazco, R. Ecoffet, S. Duzellier, J. P. David, J. G. Loquet, TIMA Laboratory & CNES
7.2 - Ground Tests of a Commercial Memory Cell Redesigned for Space Requirements: A Case Study, F. M. Roche, T. Monnier, U. of Montpellier
7.3 - A New Spice Model Dedicated to the Analysis of Transient Response of Irradiated MOSFETs for On-Line Testing, V. Pouget, H. Lapuyade, D. Lewis, Y. Deval, P. Fouillat, L. Sarger, U. of Bordeaux
7.4 - Radiation Hardened CMOS SOI/SOS Structures and ICs for Space Applications, K. O. Petrosjanc, I. A. Kharitonov, A. S. Adonin, U. of Moscow 11.10 - 11.30 Break

11.30 - 12.30 Session 8. On-Line Testing and BIST for Delay Faults
Moderator: B. Kaminska, OPMAXX

8.1 - Digital Oscillation BIST: Test of Path Delay Fault with a unique clock period, C. Dufaza, S. Bessiere, N. Lambellin, LIRMM
8.2 - On-Line Path Delay Fault Testing of Omega MINs, E. Kalligeros, M. Bellos, D. Nikolos, H. T. Vergos, U. of Patras
8.3 - On-Line Delay Testing of IP-Based Systems Via Selectively Transparent Scan, H. Kim, J.P. Hayes, U. of Michigan 12.30 - 14.00 Lunch

14.00 - 15.00 Session 9. On-Line Current and Analog On-Line Testing
Moderator: K. Roy, U. of Purdue

9.1 - A Ratiometric CMOS BICS for Off-/On-Line SOC Testing, Y. Maidon, Y. Deval, F. Verdier, F. Badets, A. Ivanov, U. of Bordeaux & U. of Britich Columbia
9.2 - Current - Based Checker for On-Line Analog BIST, J. Velasco - Medina, I. Rayane, M. Nicolaidis, TIMA Laboratory
9.3 - Extended State Modelling for Concurrent Testing of Linear Analog Systems, E. Simeu, A. W. Peters, I. Rayane, TIMA Laboratory 16.00 Social Event


Wednesday, July 7, 1999

8.30 - 9.30 Session 10. Self - Checking and Code Disjoint Circuits
Moderator: E. Boehl, Robert Bosch GmbH

10.1 - Reduced Area Overhead of the Input Parity for Code - Disjoint Circuits, A. Morosov, M. Gossel, H. Hartje, U. of Potsdam
10.2 - Efficient Design of Totally Self Checking Checker - Decoders for all Cyclic AN Codes, A. Paschalis, D. Gizopoulos, M. Psarakis, M. Nicolaidis, NCSR Demokritos & TIMA Laboratory
10.3 - Novel Domino-CMOS Strongly Code Disjoint and Strongly Fault Secure 1-out-of3 and 2-out of-3 Code Checkers, T. Haniotakis, Y. Tsiatouhas, C. Efstathiou, D. Nikolos, ISD S.A & U. of Patras 9.30 - 9.50 Break

9.50 - 11.10 Session 11. Dependability Evaluation
Moderator: M. Abramovici, Lucent Techonologies

11.1 - Software-Embedded Multilevel Fault Injection Mechanism for Evaluation of a High-Speed Network System under Windows NT, T. Liu, Z. Kalbarcyzk, R. K. Iyer, U. of Illinois
11.2 - A unified environment for the Fault Injection in embedded microprocessor - based systems, M. Rebaudengo, M. Sonza Reorda, Politecnico di Torino
11.3 - An Intelligent Tool Kit for CISS Validation, X. Zhongwei, L. Weiwei Meng, Li, Shanghai Tiedao U.
11.4 - Towards Modeling for Dependability of Complex Integrated Circuits, R. Leveugle, CSI/INPG 11.10 - 11.30 Break

11.30 - 12.50 Session 12. System Level On-Line Testing II
Moderator: D. Pradhan, Texas A&M U.

12.1 - Estimating Testability on Digital Systems Based on Weak Mutation Analysis: Preliminary Simulation Results, F. Vargas, A. Terroso, U. of Porto Allegro
12.2 - Automatically transforming high-level code for Soft - Error Detection, M. Rebaudengo, M. Sonza Reorda, Politecnico di Torino
12.3 - Combined Resource Allocation and Test Generation for On-Line Test Structures, U. Kac, F. Novak, C. Aktouf, C. Robach, LCIS/ESISAR & Jozef Stefan Inst.
12.4 - A Fundtional Test Methodology Applied to RISC Microprocessors, S.G. Sharshunov, V. Kshevnto, Far Eastern State TU 12.50 - 14.20 Lunch

14.20 - 15. 40 Session 13. Fault Tolerance Techniques
Moderator: R. Iyer, U. Illinois

13.1 - Fault Tolerant Feedforward Neural Networks with Learning Algorithm Based on Synaptic Weight Limit, N. Kamiura, Y. Hata, N. Matsui, Himeji Institute of Technology
13.2 - Modified TMR-system with reduced hardware overhead, Vl. Saposhnikov, V. Ocheretnij, V. Saposhnikov, M. Gössel, U. of Potsdam & Railway Transport State U.
13.3 - Periodic test and structural fault-tolerance: a strategy to attain high reliability in embedded parallel computers, F. Clermidy, T.Collette, M. Nicolaidis, CEA & TIMA Laboratory
13.4 - Study of a new parallel architecture dedicated to the family of the DSCC code, T. Vallino, S. Piestrak, A. Dandache, F. Monteiro, B. Lepley, U. of Metz & Wroclaw U. of Techn.