{"id":987,"date":"2024-01-29T11:53:16","date_gmt":"2024-01-29T10:53:16","guid":{"rendered":"https:\/\/orion.polito.it\/iolts\/?page_id=987"},"modified":"2026-03-26T09:44:48","modified_gmt":"2026-03-26T08:44:48","slug":"keynote","status":"publish","type":"page","link":"https:\/\/orion.polito.it\/iolts\/keynote\/","title":{"rendered":"Keynotes"},"content":{"rendered":"\n
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Architecting for Resilience at Scale: From Research to Practice<\/h2>\n<\/div><\/div>\n\n\n\n

Dr. Sudhanva Gurumurthi<\/strong> \u2013 AMD Fellow<\/strong><\/h3>\n\n\n\n
\u00a0Date TBD \u2013\u00a0\u00a0Time TBD<\/h5>\n\n\n\n


\ud83d\udcd8Abstract:<\/strong>  Computing must be reliable. From a computer architecture perspective, achieving this goal begins with understanding the root causes of faults and applying systematic, quantitative methods to improve the resilience of hardware components. This talk will illustrate this approach through two case studies. The first describes research that led to a new resilience architecture for die-stacked DRAM that was adopted into the third generation of the JEDEC High-Bandwidth Memory standard (HBM3) and incorporated in GPUs and AI accelerators deployed at scale today in data centers. The second focuses on techniques for designing and testing high-performance CPUs to improve their resilience to faults arising from silicon defects. Together, these examples highlight how principled reliability research can translate into practical impact.<\/p>\n\n\n\n

\ud83d\udc64Bio:<\/strong> Sudhanva Gurumurthi<\/strong> is a Fellow at AMD, where he is responsible for research and advanced development in Reliability, Availability, and Serviceability (RAS).  His work has impacted numerous AMD products, multiple industry standards, and external research in the field. Before joining industry, he was an Associate Professor with tenure in the Computer Science Department at the University of Virginia. Sudhanva is the recipient of an NSF CAREER Award, a Google Focused Research Award, an IEEE Computer Society Distinguished Contributor recognition, and is named to the ISCA Hall of Fame. He currently serves as the Editor-in-Chief of IEEE Computer Architecture Letters. Sudhanva received his PhD in Computer Science and Engineering from Penn State in 2005.<\/p>\n\n\n\n

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Ultra low-cost secure chips on flexible foil: challenges and opportunities<\/h2>\n<\/div><\/div>\n\n\n\n

Pr. Nele Mentens<\/strong> \u2013 KU Leuven<\/strong><\/h3>\n\n\n\n
\u00a0Date TBD \u2013\u00a0\u00a0Time TBD<\/h5>\n\n\n\n


\ud83d\udcd8Abstract:<\/strong>\u00a0\u00a0Flexible electronic devices fabricated on foil substrates are increasingly entering mainstream applications, including smart blister packaging and medical patches. A core enabling technology is the thin-film transistor (TFT), which offers the potential for ultra\u2013low-cost manufacturing. While flexible circuits provide clear benefits in terms of cost efficiency and mechanical adaptability to diverse form factors, integrating capabilities for secure communication, data processing, and storage remains a significant challenge. This talk explores these challenges and highlights recent progress in the design of secure electronic circuits on flexible substrates.<\/p>\n\n\n\n

\ud83d\udc64Bio:<\/strong>\u00a0Nele Mentens<\/strong> is a professor at KU Leuven (Belgium) and Leiden University (the Netherlands). Her research focuses on hardware security and configurable computing. She has (co-)authored more than 150 publications across conferences, journals, and books. In addition, she serves on the editorial boards of several IEEE and ACM journals and actively contributes to the organization of conferences in the fields of security and hardware design. Most recently, she served as General Chair of the FPL 2025 conference. She is currently involved in CHES 2026 as Program Chair and in DATE 2027 as Vice Program Chair.<\/p>\n","protected":false},"excerpt":{"rendered":"

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