26th IEEE International Symposium on On-Line Testing and Robust System Design

Starting from July 13, 2020. First Virtual Edition.

 Photo: Nalpes Italy / Regan Vercruysse

IOLTS 2020 Program

Opening Remarks (Live)

  • Stefano Di Carlo (Politecnico di Torino) and Michael Nicolaidis (TIMA) – General Co-Chairs
  • Dimitris Gizopoulos (University of Athens) and Dan Alexandrescu (iRoC) – Program Co-Chairs

Keynote: Towards Principled Error-Efficient Systems (Live)

 Sarita Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests span the system stack, ranging from hardware to applications. Her early work on data-race-free memory consistency models led to the memory models for the Java and C++ programming languages and forms the foundation for memory models used in most hardware and software systems today. She is also known for her work on heterogeneous computing and software-driven approaches for hardware resiliency. She is a member of the American Academy of Arts and Sciences, a fellow of the ACM and IEEE, and a recipient of the ACM/IEEE-CS Ken Kennedy award, the Anita Borg Institute Women of Vision award in innovation, the ACM SIGARCH Maurice Wilkes award, and the University of Illinois campus award for excellence in graduate student mentoring. As ACM SIGARCH chair, she co-founded the CARES movement, winner of the CRA distinguished service award, to address discrimination and harassment in Computer Science research events. She received her PhD from the University of Wisconsin-Madison and her B.Tech. from the Indian Institute of Technology, Bombay.

Sources of errors in computer systems are increasing, ranging from unintentional transient errors due to high energy particle strikes to deliberately induced errors from approximations for lower energy and/or higher performance. Traditional error resiliency techniques that mitigate all errors and purely in hardware can be unnecessarily expensive. We use the term “error efficiency” for a paradigm that allows a controlled set of errors that are acceptable to the end user’s quality of experience while maximizing efficiency metrics related to performance, power, and/or area. Error efficient “systems” provide error efficiency through co-designed layers of the system stack, including hardware, system software, and the application.
Although error-efficient systems can provide orders of magnitude benefits, there does not exist a discipline to design such systems. This talk will discuss recent work towards such a discipline, including (1) program analysis based techniques to understand the impact of hardware errors on software; (2) extending the discipline of software engineering to account for hardware errors along with software bugs, and (3) domain-specific error efficiency techniques that match the emerging era of domain-specific hardware. These ideas lay the foundation for a new era of principled error-efficient system design.

Live sessions broadcasted through Zoom on July 13th, 2020 starting at:
  • 08:00AM PDT (Los Angeles,CA, USA)
  • 11:00AM EDT (New York,NY, USA)
  • 05:00PM CEST (Rome, Italy)
  • 11:00PM CST (Beijin, China)
  • 12:0012 midnight JST (Tokyo, Japan)

Session 1: Soft Errors (On-Demand)

  • 1.1 - Single Phase Clock Based Radiation Tolerant D Flip-flop Circuit, Abhishek JAIN (ST Microelectronics Pvt. Ltd.), Andrea VEGGETTI (STMicroelectronics), Dennis CRIPPA, Antonio BENAFANTE (STMicroelectronics), Simone GERARDIN, Marta BEGATIN (Padova University)
  • 1.2 - In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops, Sarah AZIMI, Corrado DE SIO, Luca STERPONE (Politecnico di Torino)
  • 1.3 - Soft Error Tolerance of Power-Supply-Noise Hardened Latches, Yukiya MIURA (Tokyo Metropolitan Univ.), Yuya KINOSHITA (Tokyo Metropolitan Univ.)

Session 2: Robustness Evaluation (On-Demand)

  • 2.1 - Representing Gate-Level SET Faults by Multiple SEUs on RT-Level, Ahmet BAGBABA (Cadence Design Systems), Maksim JENIHHIN (Tallinn University of Technology), Raimund UBAR (Tallinn Technical University), Christian SAUER (Cadence Design Systems GmbH)
  • 2.2 - Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models, Dan ALEXANDRESCU (IROC Technologies), Aneesh BALAKRISHNAN, Thomas LANGE, Maximilien GLORIEUX (iRoC Technologies)
  • 2.3 - Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features, Thomas LANGE, Aneesh BALAKRISHNAN, Maximilien GLORIEUX (iRoC Technologies), Dan ALEXANDRESCU (IROC Technologies), Luca STERPONE (Politecnico di Torino)

Session 3: Harsh Environments (On-Demand)

  • 3.1 - A Framework and Protocol for Dynamic Management of Fault Tolerant Systems in Harsh Environments, Eduardo WEBER WACHTER, Server KASAP, Xiaojun ZHAI, Shoaib EHSAN, Klaus MCDONALD-MAIER (University of Essex)
  • 3.2 - A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications, Pablo VAZ, Patrick GIRARD, Arnaud VIRAZEL (Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM)), Hassen AZIZA (IM2NP - Aix-Marseille Université)
  • 3.3 - PISA: Power-robust Multiprocessor Design for Space Applications, Aleksandar SIMEVSKI, Oliver SCHRAPE (IHP-Leibniz-Institut fur innovative Mikroelektronik) , Carlos BENITO (Arquimea Deutschland GmbH), Milos KRSTIC (University of Potsdam), Marko ANDJELKOVIC (IHP-Leibniz-Institut fur innovative Mikroelektronik)

Session 4: Design for Security (On-Demand)

  • 4.1 - A Secure Scan Controller for Protecting Logic Locking, Quang-Linh NGUYEN, Emanuele VALEA, Marie-Lise FLOTTES, Sophie DUPUIS, Bruno ROUZEYRE (LIRMM)
  • 4.2 - Reduced Fault Coverage as a Target for Design Scaffolding Security, Irith POMERANZ (Purdue University), SANDIP KUNDU (University of Massachusetts Amherst)
  • 4.3 - Muon-Ra: Quantum random number generation from cosmic rays, Homer GAMIL, Pranav MEHTA, Eduardo CHIELLE, Adriano DI GIOVANNI, Mohammed NABEEL, Francesco ARNEODO, Michail MANIATAKOS ((New York University Abu Dhabi)

Session 5: Novel Error Detection and Correction Techniques (On-Demand)

  • 5.1 - Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit Error Detection, Christian SCHULZ-HANKE (University of Potsdam)
  • 5.2 - Encoded Check Driven Concurrent Error Detection in Particle Filters for Nonlinear State Estimation, Chandramouli AMARNATH, Md MOMTAZ, Abhijit CHATTERJEE (Georgia Institute of Technology)
  • 5.3 - An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM, Panagiota PAPAVRAMIDOU (TIMA), Michael NICOLAIDIS (TIMA Laboratory), Patrick GIRARD (LIRMM)

Session 6: Design for Reliability and Security (On-Demand)

  • 6.1 - Automatic Fault Simulators for Diagnosis of Analog Systems, Tommaso MELIS (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA), Emmanuel SIMEU (TIMA Laboratory), Etienne AUVRAY (STMicroelectronics)
  • 6.2 - Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application, Zahra KAZEMI (Grenoble INP), Mahdi FAZELI (Bogazici University), David HELY (LCIS INP GRENOBLE), Vincent BEROULLE (Grenoble Alpes University)
  • 6.3 - A Test Sensitization State Compaction Method on Controller Augmentation, Yuki IKEGAYA, Toshinori HOSOKAWA, Yuta ISHIYAMA, Hiroshi YAMAZAKI (Nihon University)

Session 7: Fault-Based Attacks and Counter Measures (On-Demand)

  • 7.1 - Temporary Laser Fault Injection into Flash Memory: Calibration, Enhanced Attacks, and Countermeasures, Kathrin GARB, Johannes OBERMAIER (Fraunhofer AISEC)
  • 7.2 - Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis, Ana LASHERAS, Ramon CANAL, Eva RODRIGUEZ (Universitat Politecnica de Catalunya), Luca CASSANO (Poli Milano)
  • 7.3 - SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features, Han WANG (University of California, Davis), Hossein SAYADI (California State University, Long Beach), Setareh RAFATIRAD, Avesta SASAN (George Mason University), Houman HOMAYOUN (University of California, Davis)

Session 8: Testing and Fault Tolerance Techniques for Autonomous Applications (On-Demand)

  • 8.1 - On the testing of special memories in GPGPUs, Josie RODRIGUEZ CONDIA, Matteo SONZA REORDA (Politecnico di Torino)
  • 8.2 - Reduced-Precision DWC for Mixed-Precision GPUs, Fernando FERNANDES DOS SANTOS (UFRGS), Marcelo BRANDALERO (Brandenburg University of Technology (B-TU)), Pedro MARTINS BASSO (UFRGS), Luigi CARRO (Universidade Federal do Rio Grande do Sul), Michael HUBNER (B-TU), Paolo RECH (UFRGS)
  • 8.3 - Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs, Cristiana BOLCHINI (Politecnico di Milano), Luca CASSANO (Poli Milano), Andrea MAZZEO, Antonio MIELE (Politecnico di Milano)

Session 9: Lifetime Management (On-Demand)

  • 9.1 - On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test, Yousuke MIYAKE, Takaaki KATO, SEIJI KAJIHARA (Kyushu Institute of Technology), Masao ASO, Haruji FUTAMI, Satoshi MATSUNAGA (PRIVATECH Inc.), Yukiya MIURA (Tokyo Metropolitan Univ.)
  • 9.2 - Leveraging reuse and endurance by efficient mapping and placement for NVM-based FPGAs, Joao Paulo DE LIMA, Rafael MOURA (Federal University of Rio Grande do Sul), Luigi CARRO (Universidade Federal do Rio Grande do Sul)

Sesion 10: Posters (On-Demand)

  • 10.1 - Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors, Basim SHANYOUR (Southern Illinois University- Carbondale), Spyros TRAGOUDAS (Southern Illinois University)
  • 10.2 - Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods, Tatsuki KURIHARA, Kento HASEGAWA, Nozomu TOGAWA (Waseda University)
  • 10.3 - An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors, Kazunari TAKASAKI, Kento HASEGAWA (Waseda University), Ryoichi KIDA (LAC Co., Ltd.), Nozomu TOGAWA (Waseda University)
  • 10.4 - A self-scrubbing scheme for embedded systems in radiation environments, Yufan LU, Xiaojun ZHAI, Sangeet SAHA, Shoaib EHSAN, Klaus MCDONALD-MAIER (University of Essex)
  • 10.5 - Yield Estimation of a Memristive Sensor Array, Vishal GUPTA (University of Rome, Tor Vergata), Saurabh KHANDELWAL (Oxford Brookes University), Giulio PANUNZI (University of Rome, Tor Vergata), Martinelli EUGENIO (University of Rome), Said HAMDIOUI (Delft University of Technology), Abusaleh JABIR (Oxford Brookes University), MARCO OTTAVI (University of Rome)
  • 10.6 - A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method, Toshinori HOSOKAWA, Kenichiro MISAWA, Hiroshi YAMAZAKI (Nihon University), Masayoshi YOSHIMURA (Kyoto Sangyo University), Masayuki ARAI (Nihon University)
  • 10.7 - Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests, Irith POMERANZ (Purdue University)

Special Session S1: Dependable Machine Learning (On-Demand)

Organizer: Muhammad Shafique, TU Wien

  • S1.1 - Dependable Artificial Intelligence and Automated Transportation, Michael Paulitsch (Intel Corp., Munich, Germany)
  • S1.2 - Error Resilient Machine Learning for Safety-Critical Systems, Karthik Pattabiraman (University of British Columbia, Canada)
  • S1.3 - Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent Faults, Muhammad Shafique (TU Wien, Austria)

Special Session S2: AI in the Support of Reliability and Functional Safety (On-Demand)

Organizer: Jean-Luc Bataillon, STMicroelectronics

  • S2.1 - Life-Time Prognostics of Dependable VLSI-SoCs using Machine-learning, Leila Bagheriye, Ghazanfar Ali, and Hans G. Kerkhoff (Testable Design and Test of Integrated Systems (TDT) Group CTIT Research Institute, University of Twente Enschede, the Netherlands)
  • S2.2 - Spiking Neuron Hardware-Level Fault Modeling, Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan (Sorbonne Université, CNRS, LIP6, Paris, France), Luis A. Camunas-Mesay, Bernabé Linares-Barrancoy (Instituto de Microelectronica de Sevilla (IMSE-CNM), CSIC y Universidad de Sevilla, Sevilla, Spain), Haralampos-G. Stratigopoulos (Sorbonne Université, CNRS, LIP6, Paris, France)
  • S2.3 - Process to Product Reliability and Functional Safety Assessment and Management, Dan Alexandrescu, Thierry Bonnoit, Maximilien Glorieux (IROC Technologies, France)

Special Session S3: Resilience and Test for Neural Computing (On-Demand)

Organizer: Muhammad Shafique, TU Wien

  • S3.1 - Testing of Spintronic-based Neuromorphic Circuits, Mehdi Tahoori (KIT, Germany)
  • S3.2 - High-level Modeling of Manufacturing Faults in Deep Neural Network Accelerators, Kanad Basu (UT Dallas, USA)
  • S3.3 - Explainability and Dependability Analysis of Learning Automata based AI Hardware using Reachability Theory, Rishad Shafik (Newcastle University, UK)

Special Session S4: Novel Analog, RF and Mixed Testing Breakthroughs (On-Demand)

Organizer: Jean-Luc Bataillon, STMicroelectronics

  • S4.1 - A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System, M. Portolan, R. S. Feitoza, G. T. Tchendjou, V. Reynaud, K. S. Kannan, M. Barragán, E. Simeu, P. Maistri, L. Anghel, R. Leveugle, S. Mir (Univ. Grenoble Alpes, CNRS, Grenoble INP1, TIMA, 38000 Grenoble, France)
  • S4.2 - Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs, F. Azaïs, S. Bernard, M. Comte, B. Deveautour, S. Dupuis, H. El Badawi, M.-L. Flottes, P. Girard, V. Kerzerho, L. Latorre (LIRMM, Univ. of Montpellier / CNRS – Montpellier, France), F. Lefèvre (NXP Semiconductors – Caen, France), B. Rouzeyre, E. Valea, T. Vayssade, A. Virazel (LIRMM, Univ. of Montpellier / CNRS – Montpellier, France)
  • S4.3 - Enhanced Limited Pin Test for Analog, “Towards IEEE1687 for Analog”, Mahmoud Abdalwahab, Tom Waayers, Willy Slendebroek (NXP Netherlands)

Special Session S5: Low Power Design vs Robustness (On-Demand)

Organizer: Patrick Girard, LIRMM/CNRS

  • S5.1 - Industrial Practices in Low-Power Robust Design, CP. Ravikumar (TI, India)
  • S5.2 - Leveraging CMOS Aging for Efficient Microelectronics Design, A.L. Hernandez Martinez, S. Khursheed and D. Rossi (University of Liverpool, UK)
  • S5.3 - Impact of Aging on Soft Error Susceptibility in CMOS Circuits, A. Prasad Shah (IIT Jammu, India), Patrick Girard (LIRMM/CNRS, France)

Special Session S6: Test, Diagnosis and Mitigation for Automotive Applications Organizer: Gurgen Harutyunyan (Synopsys) (On-Demand)

  • S6.1 Safety-Oriented Manufacturing Test and Diagnosis Solution for Automotive SoCs, M. Casarsa (STMicroelectronics), G. Harutyunyan (Synopsys), Y. Zorian (Synopsys)
  • S6.2 Full-Scale In-Field Test and Repair Solution for Automotive SoCs, Y. Abotbol (Mobileye), S. Dror (Mobileye), G. Tshagharyan (Synopsys), G. Harutyunyan (Synopsys), Y. Zorian (Synopsys)
  • S6.3 Errors Mitigation in DRAMs Contributing to Safety in Automotive and Industrial Applications, G. Boschi (Intel), E. Spano’ (Intel), H. Grigoryan (Synopsys), A. Kumar (Synopsys), G. Harutyunyan (Synopsys)