All sessions are scheduled according to the local time.
The 30th IEEE International Symposium on On-Line Testing and Robust System Design
July 3, 2023
08:00 – 08:45 Registration & Welcome Desk
08:45 – 09:00 Opening Session
09:00 – 10:00 Keynote
Moderator: Dimitris GIZOPOULOS (University of Athens)
Silent Data Corruptions at Scale
Speaker: Harish DIXIT ( Meta)
10:00-10:15 Coffee Break
10:15 – 11:15 Regular Session 1 – Fault-Tolerant Systems
Moderator: Angeliki KRITIKAKOU (Univ Rennes, Inria, IRISA – France)
- A Novel Approach to Error Resilience in Online Reinforcement Learning – Chandramouli AMARNATH, Abhijit CHATTERJEE (Georgia Institute of Technology)
Presenter: Abhijit CHATTERJEE (Georgia Institute of Technology) - Avoiding Soft Error-induced Illegal Memory Accesses in GPU with Inter-thread Communication – Riku IWAMOTO (Osaka University), Masanori HASHIMOTO (Kyoto University)
Presenter: Masanori HASHIMOTO (Kyoto University) - TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture – Raghunandana K (Indian Space Research Organisation), Varaprasad BKSVL (Dayanandasagar College of Engineering), Matteo SONZA REORDA (Politecnico di Torino), Virendra SINGH (Indian Institute of Technology Bombay)
Presenter: Virendra SINGH (Indian Institute of Technology Bombay)
11:15 – 11:30 Break
11:30 – 12:30 Regular Session 2 – Hardware Attacks and Defenses
Moderator: Ramon CANAL (Barcelona Supercomputing Center)
- ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules – Mahya MORID AHMADI (Vienna University of Technology), Lilas ALRAHIS (New York University Abu Dhabi), Ozgur SINANOGLU (NYU-Abu Dhabi), Muhammad SHAFIQUE (New York University Abu Dhabi (NYUAD))
Presenter: Mahya MORID AHMADI (Vienna University of Technology) - BALoo: First and Efficient Countermeasure dedicated to Persistent Fault Attacks – Pierre-Antoine TISSOT (Laboratoire Hubert Curien), Lilian BOSSUET (University St Etienne), Vincent GROSSO (Laboratoire Hubert Curien)
Presenter: Pierre-Antoine TISSOT (Laboratoire Hubert Curien) - On-chip SRAM Disclosure Attack Prevention Technique for SoC – Prokash GHOSH (NXP Semiconductor, Inc, USA), Yogesh GHOLAP (Indian Institute of Technology Bombay, Mumbai, India), Virendra SINGH (Indian Institute of Technology Bombay)
Presenter: Prokash GHOSH (NXP Semiconductor, Inc, USA)
12:30 – 14:00 Lunch Break
14:00 – 15:00 Special Session 1 – Frontiers of Hardware Security
Organizer: Jeyavijayan RAJENDRAN (Texas A&M)
Moderator: Mihalis MANIATAKOS (NYU Abu Dhabi)
- Learning to Protect: Reinforcement Learning for Hardware Security – Jeyavijayan RAJENDRAN (Texas A&M University)
Presenter: Jeyavijayan RAJENDRAN (Texas A&M University) - Are Machine Learning Based CAD Tools Secure? – Siddharth GARG (NYU)
Presenter: Siddharth GARG (NYU) - An integrated testbed for trojans in printed circuit boards with fuzzing capabilities – Virinchi SURABHI, Hammond PEARCE, Prashanth KRISHNAMURTHY, Ramesh KARRI, Farshad KHORRAMI and Joshua TRUJILLO.
Presenter: Farshad KHORRAMI (NYU)
15:00 – 15:10 Coffee Break
15:10 – 16:40 Special Session 2 – Silent Data Corruption & Panel
Organizer: Dimitris GIZOPOULOS (University of Athens)
Moderator: Stefano DI CARLO (Politecnico di Torino)
- Dealing with Silent Data Corruptions at Scale – Harish DIXIT (Meta)
Presenter: Harish Dixit (Meta) - Silent Data Corruptions: Microarchitectural Modeling – Dimitris GIZOPOULOS (University of Athens)
Presenter: Dimitris GIZOPOULOS (University of Athens) - Silicon Data Corruption: Investigation or Mitigation – Yervant ZORIAN (Synopsys)
Presenter: Yervant ZORIAN (Synopsys)
20:00 – 23:59 Welcome Reception
July 4, 2023
08:00 – 09:00 Registration & Welcome Desk
09:00 – 10:00 Regular Session 3 – Hardware Security and Privacy
Moderator: Sergi ALCAIDE (Barcelona Supercomputer Center)
- MPloC: Privacy-Preserving IP Verification using Logic Locking and Secure Multiparty Computation – Dimitris MOURIS, Charles GOUERT, Nektarios TSOUTSOS (University of Delaware)
Presenter: Dimitris MOURIS (University of Delaware) - On Evaluating the Security of Dynamic Scan Obfuscation Scheme – Gaurav KUMAR, Anjum RIAZ, Yamuna PRASAD, Satyadev AHLAWAT (Indian Institute of Technology Jammu)
Presenter: Satyadev AHLAWAT (Indian Institute of Technology Jammu) - Ray-Spect: Local Parametric Degradation for Secure Designs – Nasr-eddine OULDEI TEBINA (TIMA), Laurent MAINGAULT (CEA), Nacer-Eddine ZERGAINOH (TIMA), Guillaume HUBERT (ONERA), Paolo MAISTRI (CNRS)
Presenter: Nasr-eddine OULDEI TEBINA (TIMA)
10:00 – 10:15 Coffee Break
10:15 – 11:15 Regular Session 4 – Reliability on Low-Power Systems
Moderator: Fabian Vargas (IHP – Leibniz Institute for High Performance Microelectronics)
- A learning-based approach for single event transient analysis in pass transistor logic – Zhe ZHANG (Karlsruhe Institute of Technology), Zhihang WU (Huawei Technologies Co., Ltd. Shenzhen), Christian WEIS, Norbert WEHN (RPTU Kaiserslautern-Landau), Mehdi TAHOORI (Karlsruhe Institute of Technology)
Presenter: Zhe ZHANG (Karlsruhe Institute of Technology) - Microarchitecture-Aware Timing Error Prediction via Deep Neural Networks – Styliani TOMPAZI (Queen’s University Belfast), Georgios KARAKONSTANTIS (ECIT/Queen’ University)
Presenter: Georgios KARAKONSTANTIS (ECIT/Queen’ University) - On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers – Georgios CHATZITSOMPANIS (Queen’s University of Belfast), Georgios KARAKONSTANTIS (ECIT/Queen’ University)
Presenter: Georgios CHATZITSOMPANIS (Queen’s University of Belfast)
11:15 – 11:30 Break
11:30 – 12:30 Special Session 3 – Towards Dependable RISC-V Cores For Edge Computing Devices
Organizer: Marcello TRAIOLA (INRIA Rennes / IRISA Lab)
Moderator: Alessandro SAVINO (Politecnico di Torino)
- Quantum Safe Secure Boot For OpenTitan RoT Used In IoT Devices – Allan AASMA, Rafail PSIAKIS, Jari LUKKARILA, Ari KULMALA (TII – United Arab Emirates)
Presenter: Rafail PSIAKIS (TII – United Arab Emirates) - System-level Security Solutions for RISC-V – Alessandro PALUMBO, Luca CASSANO (Politecnico di Milano – Italy), Marco OTTAVI (Università degli Studi di Roma Tor Vergata – Italy and University of Twente – The Netherlands)
Presenter: Marcello TRAIOLA (INRIA Rennes / IRISA Lab) - Fine-grained Dual Core Lock-Step (DCLS) RISC-V – Romaric P. NIKIEMA, Marcello TRAIOLA, Angeliki KRITIKAKOU (Univ Rennes, Inria, IRISA – France)
Presenter: Angeliki KRITIKAKOU (Univ Rennes, Inria, Irisa)
12:30 – 14:00 Lunch Break
14:00 – 15:00 Poster Session
- ERrOR: Improving Performance and Fault Tolerance using Early Execution – Raj Kumar CHOUDHARY, Janeel PATEL, Virendra SINGH (Indian Institute of Technology Bombay)
Presenter: Rajkumar CHOUDHARY (IIT Bombay) - Experimental Evaluation of Delayed-based Detectors against Power-off Attack – Maryam ESMAEILIAN (LCIS Laboratory), Aghiles DOUADI (TIMA), Zahra KAZEMI (Univ. Grenoble Alpes, Grenoble INP, LCIS), Vincent BEROULLE (LCIS INP GRENOBLE), Amir-Pasha MIRBAHA (Grenoble INP), Mahdi FAZELI (Halmstad University), Elena Ioana VATAJELU, Paolo MAISTRI (TIMA Laboratory), Giorgio DI NATALE (TIMA)
Presenter: Vincent BEROULLE (Grenoble INP – UGA) - Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design – Yusei HONDA, Yutaka MASUDA, Tohru ISHIHARA (Nagoya University)
Presenter: Yusei HONDA (Nagoya University) - Neural Network Quantisation for Faster Homomorphic Encryption – Wouter LEGIEST (KU Leuven), Jan-Pieter D’ANVERS, Turan FURKAN, Van Beirendonck MICHIEL, Ingrid VERBAUWHEDE (COSIC – KU Leuven)
Presenter: Wouter LEGIEST (KU Leuven LRD) - Radiation-Induced Errors in the Software Level of Real-Time Soft Processing System – Corrado DE SIO, Daniele RIZZIERI, Andrea PORTALURI, Salvatore G. LA GRECA, Sarah AZIMI (Politecnico di Torino)
Presenter: Andrea PORTALURI (Politecnico di Torino) - Space Shuttle: A Test Vehicle for the Reliability of the SkyWater 130nm PDK for Future Space Processors – Ivan RODRIGUEZ-FERRANDEZ (Barcelona Supercomputer Center), Leonidas KOSMIDIS (Barcelona Supercomputing Center), Maris TALI, David STEENARI (European Space Agency)
Presenter: Ivan RODRIGUEZ-FERRANDEZ (Barcelona Supercomputer Center)
- European Projects Dissemination Opportunity
- SafeTI Traffic Injector Enhancement for Effective Interference Testing in Critical Real-Time Systems – Francisco FUENTES, Raimon CASANOVA, Sergi ALCAIDE and Jaume ABELLA (Universitat Autònoma de Barcelona, Barcelona Supercomputing Center)
- Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services – Ramon CANAL (Universitat Politècnica De Catalunya), Stefano DI CARLO (Politecnico di Torino), Dimitris GIZOPOULOS (University of Athens), Alberto SCIONTI (LINKS)
- Neuromorphic energy-efficient secure accelerators based on phase change materials augmented silicon photonics – Fabio PAVANELLO (CRNS), George PAPADIMITRIOU (University of Athens), Alessandro SAVINO (Politecnico di Torino)
15:00 – 15:10 Coffee Break
15:10 – 16:10 Regular Session 5 – On-Line Testing
Moderator: Mihalis PSARAKIS (University of Piraeus)
- ML-Based Online Design Error Localization for RISC-V Implementations – Hardi SELG, Maksim JENIHHIN, Peeter ELLERVEE, Jaan RAIK (Tallinn University of Technology)
Presenter: Hardi SELG (Tallinn University of Technology) - On the Development of Prognostics and System Health Management (PHM) Techniques for ReRAM Applications – Jose CAYO, Matias MELIVILU (Universidad Tecnica Federico Santa Maria), Antonio RUBIO (Universitat Politecnica Catalunya (UPC)), Ioannis VOURKAS (Universidad Técnica Federico Santa María)
Presenter: Ioannis VOURKAS (Universidad Técnica Federico Santa María) - SafeLS: an Open Source Implementation of a Lockstep NOEL-V RISC-V Core – Marcel SARRASECA, Sergi ALCAIDE, Francisco FUENTES, Juan Carlos RODRIGUEZ, Feng CHANG, Ilham LASFAR, Ramon CANAL (Barcelona Supercomputing Center), Francisco J. CAZORLA (Barcelona Supercomputing Center (BSC-CNS), Spanish national Research Council (IIIA-CSIC)), JAUME ABELLA (Barcelona Supercomputing Center (BSC-CNS))
Presenter: Marcel SARRASECA (Barcelona Supercomputing Center)
16:30 – 22:30 Social Event
July 5, 2023
08:00 – 09:00 Registration & Welcome Desk
09:00 – 10:00 Regular Session 6 – Physical Layer Resilience
Moderator: Mehdi TAHOORI (Karlsruhe Institute of Technology)
- On-Line Method to Limit Unreliability and Bit-Aliasing in RO-PUF – Sergio VINAGRERO GUTIERREZ, Giorgio DI NATALE (TIMA), Elena Ioana VATAJELU (TIMA Laboratory)
Presenter: Sergio VINAGRERO GUTIERREZ (TIMA Laboratory / FLORALIS) - A Study of High Temperature Effects on Ring Oscillator based Physical Unclonable Functions – Aghiles DOUADI, Giorgio DI NATALE (TIMA), Vincent BEROULLE (Grenoble Alpes University), Paolo MAISTRI, Elena Ioana VATAJELU (TIMA Laboratory)
Presenter: Aghiles DOUADI (Grenoble INP) - About the correlation between logical identified faulty gates and their layout characteristics – Lorenzo CARDONE, Giusy IARIA (Politecnico di Torino), Paolo BERNARDI (Politecnico Di Torino), Davide APPELLO, Giuseppe GAROZZO, Vincenzo TANCORRE (STMicroelectronics)
Presenter: Lorenzo CARDONE (Politecnico di Torino)
10:00 – 10:15 Coffee Break
10:15 – 11:15 Regular Session 7 – Robustness
Moderator: Alberto SCIONTI (LINKS)
- Detecting Hardware Faults in Approximate Adders via Minimum Redundancy – IOANNIS TSOUNIS, Dimitris AGIAKATSIKAS, Mihalis PSARAKIS (University of Piraeus)
Presenter: IOANNIS TSOUNIS (University of Piraeus) - Evaluation and mitigation of faults affecting Swin Transformers – Gabriele GAVARINI, Annachiara RUOSPO, Ernesto SANCHEZ (Politecnico di Torino)
Presenter: Gabriele GAVARINI (Politecnico di Torino) - Radiation Hardness Evaluations of a Stacked Flip Flop in a 22nm FD-SOI Process by Heavy-Ion Irradiation – Shotaro SUGITANI, Ryuichi NAKAJIMA, Ito TAKAFUMI, Furuta JUN, Kobayashi KAZUTOSHI (Kyoto Institute of Technology)
Presenter: Shotaro SUGITANI (Kyoto Institute of Technology)
11:15 – 11:30 Break
11:30 – 12:30 Special Session 4 – Silicon Lifetime Management
Organizer: Yervant Zorian (Synopsys)
Moderator: TBA
- Silicon Lifecycle Challenges and Opportunities – Yervant ZORIAN (Synopsys)
Presenter: Yervant Zorian (Synopsys) - SLM ISA and Hardware Extensions for RISC-V Processors – Mehdi Tahoori (Karlsruhe Institute of Technology)
Presenter: Mehdi TAHOORI (Karlsruhe Institute of Technology)
12:30 – 14:00 Lunch Break
14:00 – 15:00 Regular Session 8 – Power and Energy Optimization
Moderator: Marcello TRAIOLA (INRIA Rennes / IRISA Lab)
- Artificial Neural Network Accelerator for Classification of In-Field Conducted Noise in Integrated Circuits’ DC Power Lines – Fabian VARGAS (IHP – Leibniz Institute for High Performance Microelectronics), Douglas BORBA (LABELO – Specialized Electric-Electronic Laboratories), Juliano D’ORNELAS BENFICA (Independent Consulting Research), Rizwan Tariq SYED (IHP)
Presenter: Fabian LUIS VARGAS (IHP GmbH) - Minimum SRAM Retention Voltage: Insight About Optimizing Power Efficiency Across Temperature Profile, Process Variation and Aging – Yunus Emre ASLAN, Florian CACHO (STMicroelectronics), Lorena ANGHEL (Grenoble-INP), Tanuj KUMAR, Kedar DHORI, Ashish KUMAR, Fabien GINER, Marc FAURICHON (STMicroelectronics)
Presenter: Yunus EMRE ASLAN (STMicroelectronics) - Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization – Natalia LYLINA (University of Stuttgart), Stefan HOLST (Kyushu Institute of Technology), Hanieh JAFARZADEH, ALEXANDRA KOURFALI (University of Stuttgart), Hans-Joachim WUNDERLICH (Universitat Stuttgart)
Presenter: Hanieh JAFARZADEH (University of Stuttgart)